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Adventurer
Adventurer
218 Views
Registered: ‎04-19-2018

32-bit float in verilog?

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As far as I know Verilog 2000 has the (32-bit) shortfloat type that Vivado doesn't recognize...

Am I missing an include or is there any alias or is not possible to have 32-bit floats in Vivado?

Note: I tried both shortfloat and short float.

 

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Scholar markcurry
Scholar
171 Views
Registered: ‎09-16-2009

Re: 32-bit float in verilog?

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First - there's is no "float" nor "shortfloat" in Verilog (or SystemVerilog).  Perhaps you're thinking of "real" and "shortreal".

As to (RTL) synthesis of floating-point types - it's not supported by Vivado Synthesis (nor any synthesizer that I'm aware of).  Exceptions would be for constant calcululations only (i.e. literals or parameters)

For HLS synthesis - you'll probably better off moving or asking this question over on the HLS forums.

Regards,

Mark

 

 

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Scholar dpaul24
Scholar
210 Views
Registered: ‎08-07-2014

Re: 32-bit float in verilog?

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@satguy,

I did not find anything like that in the UG801 Vivado synthesis guide. Therefore I would conclude that it is not supported.

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Adventurer
Adventurer
199 Views
Registered: ‎04-19-2018

Re: 32-bit float in verilog?

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Neither I did. I'm interfacing HDL with AXI4-Stream IP blocks from HLS. HLS supports float streams with 32-bit data. How can one then write HDL for these?

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Scholar markcurry
Scholar
172 Views
Registered: ‎09-16-2009

Re: 32-bit float in verilog?

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First - there's is no "float" nor "shortfloat" in Verilog (or SystemVerilog).  Perhaps you're thinking of "real" and "shortreal".

As to (RTL) synthesis of floating-point types - it's not supported by Vivado Synthesis (nor any synthesizer that I'm aware of).  Exceptions would be for constant calcululations only (i.e. literals or parameters)

For HLS synthesis - you'll probably better off moving or asking this question over on the HLS forums.

Regards,

Mark

 

 

Adventurer
Adventurer
141 Views
Registered: ‎04-19-2018

Re: 32-bit float in verilog?

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True, is 'real' not 'float'

In the meantime I created another HLS IP block doing what I needed: generating some values and sending by an AXI Stream. I wanted to do it in the test bench.

 

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