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JR_97

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04-14-2021 02:51 PM

222 Views

Registered:
04-14-2021

4-bit ALU having syntax and other errors, advice needed.

I currently have a vivando project that is designed to run a 4-bit arithmetic logic unit that runs on the device Artix-7 FPGA (XC7A100TCSG324-1) with a 1-bit adder and a 1-bit alu. I am very new to vhdl and am having trouble figuring out how to set up the architectual behavior and port map for the 4-bit alu.

Does anyone know what I need change to eliminate my errors? Any help is appreciated.

4-bit alu:

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY Alu4 IS

GENERIC( CONSTANT N: INTEGER := 4; -- 4 bits ALU

CONSTANT Z: STD_LOGIC_VECTOR(3 DOWNTO 1) := "000" -- 3 Zeros

);

PORT(

a, b: IN STD_LOGIC_VECTOR(N-1 DOWNTO 0);

control: IN STD_LOGIC_VECTOR(1 DOWNTO 0);

overflow: OUT STD_LOGIC;

zero: OUT STD_LOGIC;

cOut: OUT STD_LOGIC;

result: OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0)

);

END Alu4;

ARCHITECTURE behavioral OF Alu4 IS

COMPONENT Alu1

PORT(

a: IN STD_LOGIC;

b: IN STD_LOGIC;

cIn: IN STD_LOGIC;

control: IN STD_LOGIC_VECTOR(1 DOWNTO 0);

cOut: OUT STD_LOGIC;

result: OUT STD_LOGIC

);

END COMPONENT;

SIGNAL carry_sig: STD_LOGIC_VECTOR(N DOWNTO 0); -- carry_sig(N) = MSB cOut

SIGNAL result_sig: STD_LOGIC_VECTOR(N-1 DOWNTO 0);

BEGIN ## this is where the errors are all located.

uut: Alu1 PORT MAP(a => a, b => b, cOut_sig, result_sig);

process (a, b, control)

BEGIN

case control is

WHEN "000" =>

cOut = a AND b,

WHEN "001" =>

cOut = a OR b,

WHEN "010" =>

cOut = a + b,

WHEN "011" =>

cOut = a - b,

WHEN "100" =>

cOut = NOT a,

WHEN "101" =>

cOut = a XOR b,

WHEN "110" =>

cOut = a + 1,

WHEN "111" =>

cOut = a - 1,

WHEN others =>

NULL;

END case;

END process;

END behavioral;

Also here is the 1-bit alu code:

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY Alu1 IS

PORT(

a: IN STD_LOGIC; -- Input SW[2]

b: IN STD_LOGIC; -- Input SW[1]

cIn: IN STD_LOGIC; -- Input SW[0]

control: IN STD_LOGIC_VECTOR(1 DOWNTO 0); -- Input SW[15..14]: control[1..0]

cOut: OUT STD_LOGIC; -- Output LED[1]

result: OUT STD_LOGIC -- Output LED[0]

);

END Alu1;

ARCHITECTURE behavioral OF Alu1 IS

COMPONENT Adder1

PORT (

a, b, cIn : IN std_logic;

cOut, sum : OUT std_logic);

END COMPONENT;

SIGNAL a_sig, b_sig: STD_LOGIC;

SIGNAL sum_sig, cOut_sig: STD_LOGIC;

SIGNAL result_sig: STD_LOGIC;

BEGIN

a_sig <= a;

b_sig <= NOT b WHEN control = "11" ELSE

b;

U1:Adder1 PORT MAP(a_sig, b_sig, cIn, cOut_sig, sum_sig);

WITH control SELECT

result_sig <=

a AND b WHEN "00",

a OR b WHEN "01",

sum_sig WHEN "10",

sum_sig WHEN "11",

sum_sig WHEN Others;

result <= result_sig;

cOut <= '0' WHEN control = "00" OR control = "01" ELSE

cOut_sig;

END behavioral;

and finally the 1-bit adder code:

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY Adder1 IS

PORT (

a, b, cIn : IN std_logic;

cOut, sum : OUT std_logic);

END Adder1;

ARCHITECTURE behavioral OF Adder1 IS

BEGIN

cOut <= (a and b) or ((a xor b) and cIn);

sum <= (a xor b) xor cIn;

END behavioral;

This alu is designed to run with this simulation file:

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY Alu4_tb IS

END Alu4_tb;

ARCHITECTURE simulate OF Alu4_tb IS

COMPONENT Alu4

PORT( a, b: IN STD_LOGIC_VECTOR(3 DOWNTO 0);

control: IN STD_LOGIC_VECTOR(1 DOWNTO 0);

overflow: OUT STD_LOGIC;

zero: OUT STD_LOGIC;

cOut: OUT STD_LOGIC;

result: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)

);

END COMPONENT;

SIGNAL a, b: STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL control: STD_LOGIC_VECTOR(1 DOWNTO 0);

SIGNAL overflow: STD_LOGIC;

SIGNAL zero: STD_LOGIC;

SIGNAL cOut: STD_LOGIC;

SIGNAL result: STD_LOGIC_VECTOR(3 DOWNTO 0);

BEGIN

uut: Alu4 PORT MAP(

a, b, control,

overflow, zero, cOut, result);

stimulus: PROCESS

BEGIN

-- test bench stimulus code

-- "0000" AND "0000": overflow<='0', zero<='1', cOut<='0', result<="0000"

a <= "0000"; b <= "0000"; control <= "00";

WAIT FOR 40 ns;

-- "0111" AND "0001": overflow<='0', zero<='0', cOut<='0', result<="0001"

a <= "0111"; b <= "0001"; control <= "00";

WAIT FOR 40 ns;

-- "0111" AND "1111": overflow<='0', zero<='0', cOut<='0', result<="0111"

a <= "0111"; b <= "1111"; control <= "00";

WAIT FOR 40 ns;

-- "1111" AND "0111": overflow<='0', zero<='0', cOut<='0', result<="0111"

a <= "1111"; b <= "0111"; control <= "00";

WAIT FOR 40 ns;

-- "1000" AND "0001": overflow<='0', zero<='1', cOut<='0', result<="0000"

a <= "1000"; b <= "0001"; control <= "00";

WAIT FOR 40 ns;

-- "1000" AND "1111": overflow<='0', zero<='0', cOut<='0', result<="1000"

a <= "1000"; b <= "1111"; control <= "00";

WAIT FOR 40 ns;

-- "0000" OR "0000": overflow<='0', zero<='1', cOut<='0', result<="0000"

a <= "0000"; b <= "0000"; control <= "01";

WAIT FOR 40 ns;

-- "0111" OR "0001": overflow<='0', zero<='0', cOut<='0', result<="0111"

a <= "0111"; b <= "0001"; control <= "01";

WAIT FOR 40 ns;

-- "0111" OR "1111": overflow<='0', zero<='0', cOut<='0', result<="1111"

a <= "0111"; b <= "1111"; control <= "01";

WAIT FOR 40 ns;

-- "1111" OR "0111": overflow<='0', zero<='0', cOut<='0', result<="1111"

a <= "1111"; b <= "0111"; control <= "01";

WAIT FOR 40 ns;

CMPS375 (Lab 4) Page 5 / 10 Dr. Kuo-pao Yang

-- "1000" OR "0001": overflow<='0', zero<='0', cOut<='0', result<="1001"

a <= "1000"; b <= "0001"; control <= "01";

WAIT FOR 40 ns;

-- "1000" OR "1111": overflow<='0', zero<='0', cOut<='0', result<="1111"

a <= "1000"; b <= "1111"; control <= "01";

WAIT FOR 40 ns;

-- "0000" ADD "0000": overflow<='0', zero<='1', cOut<='0', result<="0000"

a <= "0000"; b <= "0000"; control <= "10";

WAIT FOR 40 ns;

-- "0111" ADD "0001": overflow<='1', zero<='0', cOut<='0', result<="1000"

a <= "0111"; b <= "0001"; control <= "10";

WAIT FOR 40 ns;

-- "0111" ADD "1111": overflow<='0', zero<='0', cOut<='1', result<="0110"

a <= "0111"; b <= "1111"; control <= "10";

WAIT FOR 40 ns;

-- "1111" ADD "0111": overflow<='0', zero<='0', cOut<='1', result<="0110"

a <= "1111"; b <= "0111"; control <= "10";

WAIT FOR 40 ns;

-- "1000" ADD "0001": overflow<='0', zero<='0', cOut<='0', result<="1001"

a <= "1000"; b <= "0001"; control <= "10";

WAIT FOR 40 ns;

-- "1000" ADD "1111": overflow<='1', zero<='0', cOut<='1', result<="0111"

a <= "1000"; b <= "1111"; control <= "10";

WAIT FOR 40 ns;

-- "0000" SUB "0000": overflow<='0', zero<='1', cOut<='1', result<="0000"

a <= "0000"; b <= "0000"; control <= "11";

WAIT FOR 40 ns;

-- "0111" SUB "0001": overflow<='0', zero<='0', cOut<='1', result<="0110"

a <= "0111"; b <= "0001"; control <= "11";

WAIT FOR 40 ns;

-- "0111" SUB "1111": overflow<='1', zero<='0', cOut<='0', result<="1000"

a <= "0111"; b <= "1111"; control <= "11";

WAIT FOR 40 ns;

-- "1111" SUB "0111": overflow<='0', zero<='0', cOut<='1', result<="1000"

a <= "1111"; b <= "0111"; control <= "11";

WAIT FOR 40 ns;

-- "1000" SUB "0001": overflow<='1', zero<='0', cOut<='1', result<="0111"

a <= "1000"; b <= "0001"; control <= "11";

WAIT FOR 40 ns;

-- "1000" SUB "1111": overflow<='0', zero<='0', cOut<='0', result<="1001"

a <= "1000"; b <= "1111"; control <= "11";

WAIT FOR 40 ns;

WAIT;

END PROCESS;

END simulate;

3 Replies

richardhead

Scholar

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04-15-2021 01:21 AM

171 Views

Registered:
08-01-2012

You have a couple of problems in this code:

1.

`uut: Alu1 PORT MAP(a => a, b => b, cOut_sig, result_sig);`

You have positional association after named association. This is illegal. Positional must be used before named association. I recommended using named association for ALL mappings in a port map. You have also not mapped any output signals from the component, and signals you have mapped do not correspond to the correct ports. Hence why named assiciation is ALWAYS recommended.

2. You have a lot of arithmetic functions on std_logic. There are no functions defined for "+" "-" etc. on a single std_logic. I recommend reading up on the VHDL package numeric_std, and how to use it. If you can use VHDL 2008, you can also consider numeric_std_unsigned. std_logic_unsigned should not be used as it is not a VHDL standard.

bruce_karaffa

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04-15-2021 02:46 AM

152 Views

Registered:
06-21-2017

maps-mpls

Mentor

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04-15-2021 10:25 PM

108 Views

Registered:
06-20-2017

Also, when pasting code, use the </> symbol, or click on the HTML graphic, and insert your code between a <pre> </pre>. It would allow more people to quickly ascertain what is going on in your code.

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