12-22-2019 03:16 AM
I m new to the FPGA. I m doing a fft for my college project. My design is working properly in simulation. Moreover, I did post-synthesis timing simulation and fixed some problems in here. Beside that, I did not get any considerable warning in simulation and implementation. However, my design does not work properly, and when I try to debug some signals, They does not apper when I work the device. Therefore, If someone can help me, I would be very happy for that.
12-22-2019 04:17 AM - edited 12-22-2019 09:56 AM
Without any more details, it will be difficult to guess at what problem you are having. Here's some background material therefore that might help
The designs listed above are entirely open source, and you are free to download and try them.
Let me ask, though, are you trying to build an FFT yourself, or just use Xilinx's FFT? Similarly, how extensive was your simulation? Did you try placing tones into your FFT and observe the right result? How about impulses? Did you check whether or not the impulse results had the amplitude you were expecting? The frequency you were expecting? Was there any clipping? All of these were checks of my own when testing the FFT that I wrote myself, and valuable checks as well.
I've also replied to several folks on Digilent's forums discussing how to find/solve/fix problems like this. Have you checked to see whether your issue has been found elsewhere?
In another article, I discuss how to go about debugging a design with an FFT in it. The approach is straightforward and common to most engineering disciplines: divide the problem into pieces, and then examine each piece to see which one has the problem. If you are convinced your simulation looks good, then you may need to do this in hardware. Xilinx provides a means of extracting a trace from a running design which you might find valuable for this purpose. If you aren't familiar with how to do that, then it's really time to learn. Traces aren't the only things you can extract. Sometimes it helps to calculate values and extract them--things like the maximum and minimum values going into an FFT can give you an idea of whether or not there might be scaling issues within or not. Further, in a recent article I argue for placing counters at the inputs and outputs of any signal processing routine to make certain data aren't getting added or dropped. Are you doing this? Have you verified that you aren't dropping data? That the data coming from your signal source (whatever that is) is good?
Again, there's just so many things that can go wrong, and such a paucity of details listed above, that it's hard to be certain what problem you are suffering from.
12-23-2019 04:47 PM
Thank you very much for replying me. Actually I found a very crucial mistake that is in the butterfly modules. After that, my design is working properly in test bench. However, I noticed that in the timing simulation, there is an interesting error about writing data from FIFO's and BRAM's. Moreover, my outputs are different from outputs in the simulation(test bench). Therefore, some inputs are appearing wrong. The warning is " $setuphold (posedge WRCLK, negedge DI, (0:0:0), (0:0:0),, wren_enable_p, wren_enable_p, WRCLK_dly, DI_dly)". When I start to take data from RAM's, I m first giving the write enable and taking the output, but there is something wrong about my method. Therefore, what should I do? One idea that I should wait one more cycle to take input. Is it a proper answer? If you give me an expert answer, I would be very appreciated. (Note : I m using FIFO MACRO and BRAM MACRO, with instantation files)
My best regards,