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Newbie alexmakarov
Newbie
569 Views
Registered: ‎07-13-2018

7-serives issue. FD and FD_1 are optimised into IDDR

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I am trying to implement Xapp1015 on a 7-series device. 

I am encountering  a problem when FD and FD_1 are optimised into IDDR by Vivado.

 

 

My code explicitly instantiates FDs and FD_1s  which then location constrained in the XDC as follows:

 

QF0 : FD_1
port map (
Q => QF(0), -- Data output
C => CLK270(0), -- Clock input
D => asi_rx -- Data input
);
QF1 : FD_1
port map (
Q => QF(1), -- Data output
C => CLK270(1), -- Clock input
D => asi_rx -- Data input
);
QF2 : FD_1
port map (
Q => QF(2), -- Data output
C => CLK270(2), -- Clock input
D => asi_rx -- Data input
);
QF3 : FD_1
port map (
Q => QF(3), -- Data output
C => CLK270(3), -- Clock input
D => asi_rx -- Data input
);

QR0 : FD
port map (
Q => QR(0), -- Data output
C => CLK270(0), -- Clock input
D => asi_rx -- Data input
);
QR1 : FD
port map (
Q => QR(1), -- Data output
C => CLK270(1), -- Clock input
D => asi_rx -- Data input
);
QR2 : FD
port map (
Q => QR(2), -- Data output
C => CLK270(2), -- Clock input
D => asi_rx -- Data input
);
QR3 : FD
port map (
Q => QR(3), -- Data output
C => CLK270(3), -- Clock input
D => asi_rx -- Data input
);

 

My XDC constraints:

 

set_property LOC SLICE_X0Y73 [get_cells {*/u_asi_lvds_rx/dru_8phase/QR0}];
set_property LOC SLICE_X0Y74 [get_cells {*/u_asi_lvds_rx/dru_8phase/QF0}];
set_property LOC SLICE_X1Y73 [get_cells {*/u_asi_lvds_rx/dru_8phase/QR1}];
set_property LOC SLICE_X1Y74 [get_cells {*/u_asi_lvds_rx/dru_8phase/QF1}];
set_property LOC SLICE_X2Y73 [get_cells {*/u_asi_lvds_rx/dru_8phase/QR2}];
set_property LOC SLICE_X2Y74 [get_cells {*/u_asi_lvds_rx/dru_8phase/QF2}];
set_property LOC SLICE_X3Y73 [get_cells {*/u_asi_lvds_rx/dru_8phase/QR3}];
set_property LOC SLICE_X3Y74 [get_cells {*/u_asi_lvds_rx/dru_8phase/QF3}];

 

The result is that QR0 and QR1 are optimised into IDDR and are not placed into X0Y73 and X0Y77 as specified in the XDC.

 

pacement.jpg 

 

 

 A solution was proposed here for ISE and a Spartan Device:

https://forums.xilinx.com/t5/Spartan-Family-FPGAs/Spartan-6-issue-FD-FD-1-optimized-to-an-IDDR2/td-p/467374

 

However it does not seem to work in Vivado and Virtex-7.    How do I prevent a FD and FD_1 being optimised into IDDR?

 

Please advise.

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1 Solution

Accepted Solutions
Historian
Historian
619 Views
Registered: ‎01-23-2009

Re: 7-serives issue. FD and FD_1 are optimised into IDDR

Jump to solution

You could try putting a DONT_TOUCH property on the flip-flops, but I am not sure this is the best approach...

 

Trying to oversample a signal by using multiple flip-flops with different clock phases is not very precise - the delay of routing from the IBUF to the different flip-flops is hard to control (as you are seeing).

 

A better solution is to oversample it with only one sampling device - the most obvious choice is the ISERDES. The ISERDES already has an "OVERSAMPLE" mode, which allows you to get 4 samples per "clock"as long as you have both a 0degree and 90degree version of the same clock (through the same type of clock buffer). Alternatively, (unless the frequency is too high), you can generate a 1x clock and a 4x clock, and use the ISERDES in 8:1 deserialization with DDR mode - this will generate 8 evenly spaced samples of your incoming signal in one low speed clock.

 

Avrum

2 Replies
Historian
Historian
620 Views
Registered: ‎01-23-2009

Re: 7-serives issue. FD and FD_1 are optimised into IDDR

Jump to solution

You could try putting a DONT_TOUCH property on the flip-flops, but I am not sure this is the best approach...

 

Trying to oversample a signal by using multiple flip-flops with different clock phases is not very precise - the delay of routing from the IBUF to the different flip-flops is hard to control (as you are seeing).

 

A better solution is to oversample it with only one sampling device - the most obvious choice is the ISERDES. The ISERDES already has an "OVERSAMPLE" mode, which allows you to get 4 samples per "clock"as long as you have both a 0degree and 90degree version of the same clock (through the same type of clock buffer). Alternatively, (unless the frequency is too high), you can generate a 1x clock and a 4x clock, and use the ISERDES in 8:1 deserialization with DDR mode - this will generate 8 evenly spaced samples of your incoming signal in one low speed clock.

 

Avrum

512 Views
Registered: ‎01-22-2015

Re: 7-serives issue. FD and FD_1 are optimised into IDDR

Jump to solution

Hi Alex,

 

I am able to make things work for Kintex-7 (which should be similar to Virtex-7) by doing the following:

 

As suggest in the referenced Spartan-6 post, your VHDL should have something like the following:

    signal QF, QR : std_logic_vector(3 downto 0);
    
    ATTRIBUTE IOB : string;
    ATTRIBUTE IOB of QF, QR : signal is "FALSE";

 

Next, your XDC LOC constraints should be similar to the following:

set_property LOC SLICE_X0Y73 [get_cells {*/u_asi_lvds_rx/dru_8phase/QR_reg[0]}];
set_property LOC SLICE_X0Y74 [get_cells {*/u_asi_lvds_rx/dru_8phase/QF_reg[0]}];
...
...

...note use of QR_reg[0] and QF_reg[0] instead of QR0 and QF0 (that you used).

 

 

Please consider Avrum's suggestions about ISERDES.

 

Mark