09-04-2020 01:15 AM
I am trying to synthesize a top module systemverilog design. It has various submodules. all submodules are synthesized correctly. Everything seems fine but when I try to synthesize top module, I am getting "submodule "xyz" not found" error. Any idea please?
09-04-2020 01:31 AM
Here it is: also there is a conditional expression could not be resolved as constant error although the expression is purely logical:
like (genvar i=0;i<3;i=i+1)
09-04-2020 05:27 AM
Do you see any missing sources in the project when you select this button in GUI?
The greying out tells us that these files are a part of conditional if generate code and they are not instantiated as per your conditional if generate code
For example, see the down-counter file in the below snapshot