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msaideroglu
Observer
Observer
800 Views
Registered: ‎11-19-2018

[8-439] submodule not found error

I am trying to synthesize a top module systemverilog design. It has various submodules. all submodules are synthesized correctly. Everything seems fine but when I try to synthesize top module, I am getting "submodule "xyz" not found" error. Any idea please?

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6 Replies
surajc
Xilinx Employee
Xilinx Employee
799 Views
Registered: ‎01-30-2019

Hi @msaideroglu 

Can you show us the hierarchy of your design, from the hierarchy window? 

surajc_0-1599207469871.png

 

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msaideroglu
Observer
Observer
787 Views
Registered: ‎11-19-2018

Here it is: also there is a conditional expression could not be resolved as constant error although the expression is purely logical:

like (genvar i=0;i<3;i=i+1)

Screenshot from 2020-09-04 11-26-11.pngScreenshot from 2020-09-04 11-26-32.png

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msaideroglu
Observer
Observer
753 Views
Registered: ‎11-19-2018

All submodules can be generated seperately. Those submodules are grayed out at bottom. Is there any meaning?  

Screenshot from 2020-09-04 15-01-19.png

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surajc
Xilinx Employee
Xilinx Employee
747 Views
Registered: ‎01-30-2019

Hi @msaideroglu 

Do you see any missing sources in the project when you select this button in GUI? 

surajc_1-1599222241648.png

The greying out tells us that these files are a part of conditional if generate code and they are not instantiated as per your conditional if generate code

For example, see the down-counter file in the below snapshot

surajc_2-1599222429445.png

 

 

 

 

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msaideroglu
Observer
Observer
731 Views
Registered: ‎11-19-2018

There is no missing file. In this project, when I set top all modules seperately, it can be synthesized.
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anusheel
Moderator
Moderator
639 Views
Registered: ‎07-21-2014

@msaideroglu 

Can you please share the snippet of the generate block, if possible please share a testcase?

Thanks
Anusheel  

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