A question about vivado 2014.4 synthesize problem

[farnam]

Recently I transfer my ISE artix7 200t project to vivado 2014.4 . The reason of my migration was the slowing speed of tye bit file generating (about 4 hours) in ISE. Even though my project in vivado 2014.4 synthesized and implemented faster ( whole phasese about 40 mins completed) but my behavior logic did not work truly. I traced the problem and reached to a very confusing event. I have a FSM which rolls as a Data Manager. In this process I have a mem address pointer which in each of particular state points to specific address. The problem is when number of states have been increased the mem address pointer do not work properly or do not updated in that particular state . For example in one state I set it to 0x0004 but it did not change to that value in next state. The problem will be eliminated by decreasing the number of states.
Best regards.

[austin]

f,

What does your timing report say?

What warnings are reported?

[farnam]

There is no timing violation in my timing reports.
But I have many warnings which most of them are irrelevant to the "memory pointer" ( the signal which doesn't update in particular state).
Is there any possibility that I have a problem in another logic section and the recent issue is its sub effect.
Best regards.

[geoffbarnes]

Is this a verilog design?  Are you adding states to an FSM?  If so, just make sure the state register is wide enough.

[farnam]

Hi
No it is VHDL.
Yes when I add more states to an FSM my pointer signal will crash.
Number of state which I used is about 50. But it will work only with 32 state. In other word I have a sub module which I used it as mem interface and top module of it has 50 states. In each states I generate a mem access request with particular mem pointer. He problem is when I use more than about 32 states my pointer signal will crash and doesn't valued proper value which has been set on a particular state!
But when I decrease the number of state to lower than 32 then it works.

[farnam]

How can I know the state register is wide ??

[geoffbarnes]

You should be able to find the state register in the synthesis or implemented design and see how wide it is ... it might be encoded as opposed to one-hot for example.

The FSM should be reaching all its states.. a simulation or some chipscope can help verify that.   If not, then the FSM needs to be fixed first!  If the FSM is ok, then the pointer logic might be the problem.

[farnam]

Hi Geoff
I read synthesize and implement logs and see corresponding FSM encoder which is on hot. I exactly know where my problem is ! My design has a Base FSM which is big enough and also in each of its state I have another state machine which in each its state I initialize the mem pointer signal. I think this huge multiplexer induce a stress on vivado implementer engine. And my mem pointer will crash and could not update properly. But why I have not such a problem in ISE and it works well.
Best resgards