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Adventurer
Adventurer
4,427 Views
Registered: ‎11-18-2013

AR# 58609 Implementation: Connecting input ports to virtual grounds

Hello,

     I have a design that was originally built for a larger FPGA which now needs to be ported to a smaller device. 

Due to the lack of required number of pins, letting Vivado auto-assign the unused ports to pins isn't working (implementation reports the same). 

Upon searching for a work-around I found AR# 58609. I ran the script as it is but got an error saying that "No open design". 

So I opened the synthesized design (from Vivado's flow navigator) and ran the script. 

This time however I get the following error (no ports matched)

 

WARNING: [Vivado 12-584] No ports matched '<input_array>'.
WARNING: [Vivado 12-1023] No nets matched for command 'get_nets -of [get_ports {<input_array>}]'.

 

input_array is defined as input_array : in std_logic_vector(15 downto 0);  in top level entity. 

 

What I want to do is selectively connect some of the input_array lines to ground (so synthesis translate_off approach will not work). 

In other words, input_array<3>, input_array<7> and so on need to be grounded. 

When I run get_ports, input_array does show up. So I feel I am not opening the right design before running the tcl script. 

 

Thank you for your time,

 

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5 Replies
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Moderator
Moderator
4,422 Views
Registered: ‎07-01-2015

Re: AR# 58609 Implementation: Connecting input ports to virtual grounds

Hi @shashankm,

 

You can declare them as internal signal and use VIO to verify the functionality.

Thanks,
Arpan
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Adventurer
Adventurer
4,417 Views
Registered: ‎11-18-2013

Re: AR# 58609 Implementation: Connecting input ports to virtual grounds

Hello Arpan,

          The problem is that the input is an array and I need to "disable" only some of the signals so I am not sure if that approach would work. 

Btw, by VIO I suppose you mean hard coding the signals to a particular state. Am I correct?

Regards,

 

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Adventurer
Adventurer
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Registered: ‎11-18-2013

Re: AR# 58609 Implementation: Connecting input ports to virtual grounds

Hello,

    I tried the signal approach but there is another problem. The input signals are LVDS and are connected to IBUFDS and making them constant is throwing errors. Also, I tried copying signals to the nets that are not connected externally but again get errors related to placement (as things overlap).

Please advise,

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Moderator
Moderator
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Registered: ‎07-01-2015

Re: AR# 58609 Implementation: Connecting input ports to virtual grounds

Hi @shashankm,

 

As these pins are connected to IBUFDS try assigning to package pins whereas you can try driving other signals through VIO

Thanks,
Arpan
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Adventurer
Adventurer
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Registered: ‎11-18-2013

Re: AR# 58609 Implementation: Connecting input ports to virtual grounds

I could try doing that. However a few things that I need your input on:

There are 4 other banks that are available: two are at 3.3V, one at 1.8V & one at 1.5V. 

Will it harm the FPGA if the auto pin assignment is enabled? So essentially LVDS input pins in the FPGA are placed in banks having the above voltages. 

 

If I do the above, I get the following error during bit stream generation:

  • [Drc 23-20] Rule violation (UCIO-1) Unconstrained Logical Port - 48 out of 119 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1].

Please advise. 

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