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Adventurer
Adventurer
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Registered: ‎04-26-2019

AXI custom ip with microblaze

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Hi,

I am trying to create a custom AXI lite slave IP connected to a microblaze.

I have implemented this tutorial (multiplier custom AXI IP): http://www.fpgadeveloper.com/2014/08/creating-a-custom-ip-block-in-vivado.html

It worked, BUT, only once.

If i add a while(1) loop and do some sequential operations, the value register value read from the AXI bus is always the same, even if i change the multiplier input.

I tried this design on a KC705 eval board.

BR

 

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Scholar
Scholar
646 Views
Registered: ‎05-21-2015

@nicolas,

Sadly, this particular core has known issues.

Here's a trace (attached) that I was able to generate using this core.

known-issues.png

There are problems in both the read and write paths in this trace.  In both cases, the problem is associated with accepting a second request while BVALID & !BREADY (for the write path) or RVALID & !RREADY for the read path.  In either case, the return for the first request gets dropped and the return is replaced by the return for the second address.

This could easily explain why, in your case, you were only able to get a first return--the subsequent returns were then dropped.

Dan

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known-issues.png
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Scholar
Scholar
647 Views
Registered: ‎05-21-2015

@nicolas,

Sadly, this particular core has known issues.

Here's a trace (attached) that I was able to generate using this core.

known-issues.png

There are problems in both the read and write paths in this trace.  In both cases, the problem is associated with accepting a second request while BVALID & !BREADY (for the write path) or RVALID & !RREADY for the read path.  In either case, the return for the first request gets dropped and the return is replaced by the return for the second address.

This could easily explain why, in your case, you were only able to get a first return--the subsequent returns were then dropped.

Dan

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known-issues.png
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Adventurer
Adventurer
493 Views
Registered: ‎04-26-2019

@dgisselq,

Today, I just tested the same custom IP on a Virtex 7 (VC707 board) and I notice that I do not have any problems anymore.

So I am confused since it is generated code problem related. Perhaps, this problem has been fixed with the new Vivado release 2019.1.1 ?

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Adventurer
Adventurer
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Registered: ‎04-26-2019

I did not notice any codes changes in the "xxx_ip_S00_AXI.vhd" with the new vivado release.

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Scholar
Scholar
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Registered: ‎05-21-2015

The last release I checked was 2018.3, and the bug was still there although the design had been edited.

Dan

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Adventurer
Adventurer
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Registered: ‎04-26-2019

@dgisselq 

Ok, Thank you, I will investigate.

BR

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