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yinyadong
Observer
Observer
966 Views
Registered: ‎06-06-2017

Abnormal program termination (11)

Hi I come across an Start Timing Optimization "Abnormal program termination (11)". Every time I run synthesis, I get this massage. I tried different strategy and tried reset/re-launch synthesis. Nothing works. --------------------------------------------------------------------------------- WARNING: [Synth 8-3332] Sequential element (clk_gen_aon/fmul_gate/cken_latch_reg) is unused and will be removed from module ctrl_top. WARNING: [Synth 8-3332] Sequential element (u_asib_ahb2axi_ahb/FSM_onehot_ahb_lock_state_reg[2]) is unused and will be removed from module pl301_asib_ahb2axi_ahb2axi. WARNING: [Synth 8-3332] Sequential element (u_asib_ahb2axi_ahb/FSM_onehot_ahb_lock_state_reg[1]) is unused and will be removed from module pl301_asib_ahb2axi_ahb2axi. WARNING: [Synth 8-3332] Sequential element (u_asib_ahb2axi_ahb/FSM_onehot_ahb_lock_state_reg[0]) is unused and will be removed from module pl301_asib_ahb2axi_ahb2axi. WARNING: [Synth 8-326] inferred exception to break timing loop: 'set_false_path -through adpi_38/bclk1_out' WARNING: [Synth 8-326] inferred exception to break timing loop: 'set_false_path -through adpi_38/bclk0_out' WARNING: [Synth 8-326] inferred exception to break timing loop: 'set_false_path -through adpi_38/mclko' Inferred a: "set_disable_timing -from a -to z i_0/i_97(tricell)" Abnormal program termination (11) Please check '/proj/lark/yyin2/fpga_emulation/fpga_lark/vivado/fpga_lark.runs/synth_1/hs_err_pid21123.log' for details Can I any one give any suggestion? Regards, Yadong
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5 Replies
dpaul24
Scholar
Scholar
953 Views
Registered: ‎08-07-2014

@yinyadong,

Possibly your logic is not toggling or some outputs are unconnected so that synthesis engine is optimizing them away. Look in to the detailed synthesis report for further information.

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aher
Xilinx Employee
Xilinx Employee
884 Views
Registered: ‎07-21-2014

Hi @yinyadong 

Crash during timing optimization can occur if there is any issue with constraints written.

Can you disable xdc file and run synthesis to see if it passes?

Also please share the synthesis log file and hs_err_pid*.log file

 

-Shreyas

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dror_m
Observer
Observer
868 Views
Registered: ‎06-19-2019

Vivado 2020.1?

i had the same issue.

the problem was with  a general false path constraint that was using -through. this is Vivado issue that they will fix but for now just remove the constraint and write it more specific from clock to input pin

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viviany
Xilinx Employee
Xilinx Employee
851 Views
Registered: ‎05-14-2008

Which Vivado version are you using?

First, check if it is due to out of memory.

Second, you have timing loops in your design and the tool is trying to infer set_false_path -through constraints which may cause the issue.

set_false_path -through adpi_38/bclk1_out

set_false_path -through adpi_38/bclk0_out

According to the signal name bclk1_out and bclk0_out, try to find the combinational loop in your design and try to modify the RTL code to avoid the loop.

Just my two cents.

You can also try different version of Vivado to see if Synthesis can complete. Then you may find more clues for the timing loop in the Synthesized design.

-vivian

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yinyadong
Observer
Observer
816 Views
Registered: ‎06-06-2017

Hi All, It seems that the error is relate with ports. I delete some ports in design, then the error disappear. I have not figure out what the deleted ports affect. I will post it here when I figure it out. Thanks, Yadong