06-22-2020 01:13 AM
06-22-2020 01:43 AM
Possibly your logic is not toggling or some outputs are unconnected so that synthesis engine is optimizing them away. Look in to the detailed synthesis report for further information.
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06-23-2020 12:56 AM
Crash during timing optimization can occur if there is any issue with constraints written.
Can you disable xdc file and run synthesis to see if it passes?
Also please share the synthesis log file and hs_err_pid*.log file
06-23-2020 01:33 AM
i had the same issue.
the problem was with a general false path constraint that was using -through. this is Vivado issue that they will fix but for now just remove the constraint and write it more specific from clock to input pin
06-23-2020 02:26 AM
Which Vivado version are you using?
First, check if it is due to out of memory.
Second, you have timing loops in your design and the tool is trying to infer set_false_path -through constraints which may cause the issue.
set_false_path -through adpi_38/bclk1_out
set_false_path -through adpi_38/bclk0_out
According to the signal name bclk1_out and bclk0_out, try to find the combinational loop in your design and try to modify the RTL code to avoid the loop.
Just my two cents.
You can also try different version of Vivado to see if Synthesis can complete. Then you may find more clues for the timing loop in the Synthesized design.
06-23-2020 11:50 PM