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Participant matic
Participant
1,293 Views
Registered: ‎09-26-2016

About one-hot FSM encoding

Hi,

 

I would like to ask a question regarding FSM encoding, in case if I set "-fsm_extraction" setting in Vivado to "one hot". Let say that I define FSM states as an enum:

 

 

enum
{
Idle,
State_1,
State_2,
State_3
} State;

And my sequential always block where next state is assigned looks something like this:

 

 

always_ff @(posedge CLK or negedge RST)
{
  if(!RST)
    State <= Idle;
  else
    case(State)
      Idle:    State <= In1 ? State_1 : Idle;
      State_1: State <= In2 ? State_2 : State_1;
      State_2: State <= State_3;
      State_3: State <= Idle;
    endcase
}

Does synthesizer actually creates enum variables in one-hot manner and does it actually compare just a single bit for the case statement?

 

 

Or do I have to define enum and than write case statement as shown below: Even if "-fsm_extraction" is set to "one-hot".

 

enum
{
Idle = 4'b0001,
State_1 = 4'b0010,
State_2 = 4'b0100,
State_3 = 4'b1000
} State;
case(1'b1)
State[0]: State <= In1 ? State_1 : Idle; State[1]: State <= In2 ? State_2 : State_1; State[2]: State <= State_3; State[3]: State <= Idle; endcase

I am interested especially in FSM speed.

 

Thank you.

 

 

 

 

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3 Replies
Scholar jmcclusk
Scholar
1,276 Views
Registered: ‎02-24-2014

Re: About one-hot FSM encoding

If you want higher speed,  leave the enumeration as a symbolic list, and don't assign one-hot state values to the states.  I also recommend that you use sequential encoding, as this almost always produces higher speeds for reasonably complicated state machines.   

 

(* fsm_encoding = “sequential” *) reg [7:0] my_state;

Don't forget to close a thread when possible by accepting a post as a solution.
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Participant matic
Participant
1,241 Views
Registered: ‎09-26-2016

Re: About one-hot FSM encoding

Hi @jmcclusk:

 

Thank you for your reply. "Sequential" is meant here as a normal binary counter, or anything else?

 

So, if understand, you suggest to define states as a parameters (or localparams) as:

localparam Idle    = 2'd0;
localparam State_1 = 2'd1;
localparam State_2 = 2'd2;
localparam State_3 = 2'd3;

(* fsm_encoding = “sequential” *) logic [1:0] State = Idle;

 Ok, this example is the most trivial as it can possibly be, but is this the correct way?

 

Enumerators are quite handy, because if you add another state into the FSM, you don't have to bother with state values.

 

Thank you.

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Scholar jmcclusk
Scholar
1,208 Views
Registered: ‎02-24-2014

Re: About one-hot FSM encoding

Your example looks fine.  In SystemVerilog, no values are needed for the states, they can be purely symbolic.

Don't forget to close a thread when possible by accepting a post as a solution.
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