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Visitor
Visitor
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Registered: ‎05-09-2019

Additional debug output during Vivado synthesis

Vivado synthesis of a design using complex VHDL takes 9 hours. Of these 7.5 hours are spent doing rtl elaboration, most of the time with nothing printed on the screen or in the log file. I am using Vivado v2018.3.

1) Is there a way to turn on additional log output so I can identify which rtl causes the long elaboration time ?

2) Reading other posts it seems Vivado synthesis elaboration cannot be parallelized. Can somebody confirm this ?

 

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Scholar
Scholar
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Registered: ‎08-07-2014

@abregnsbo,

2) Reading other posts it seems Vivado synthesis elaboration cannot be parallelized. Can somebody confirm this ?

Synthesis can be multithreaded so that lesser time is needed for the result.

See this : https://forums.xilinx.com/t5/Installation-and-Licensing/Vivado-makes-use-of-CPU/td-p/821980

But are you sure that "7.5 hours are spent doing rtl elaboration" is legal and there is no problem with your VHDL coding style?

To me it seems toooo long.

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Visitor
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Registered: ‎05-09-2019

Not sure whay you mean by "... is legal".

There are no errors during elaboration, and synthesis finishes with a netlist. The VHDL is a modified version of old rtl that has been implemented in many ASICs with various ASIC synthesis tools (Design Compiler, Genus, Talus RTL). However, like you, I suspect that there is some VHDL coding style which trips up Vivado elaboration. I only whish Vivado could tell what it is currently doing.

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Scholar
Scholar
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Registered: ‎08-07-2014

@abregnsbo,

The VHDL is a modified version of old rtl that has been implemented in many ASICs with various ASIC synthesis tools (Design Compiler, Genus, Talus RTL).

Thats where problems come in. For e.g. is the RTL coding properly pipelined?

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Xilinx Employee
Xilinx Employee
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Registered: ‎05-14-2008

I'm afraid there is no way to print more info at the elaboration phase.

One thing you can try is to follow the debugging method in the following blog. The method is for debugging a crash issue. Although your issue is not a crash, you can use the same method to debug.

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Vivado-Synthesis-Crash-Debugging-Guide/ba-p/946862

Refer to "Using the black box method" or "making an individual module a "top-module" for synthesis".

You don't need to go through the whole synthesis process.

Since the issue is with RTL elaboration, you can just run "Open Elaborated Design", which will only run RTL elaboration and then open the elaborated design.

-vivian

 

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Scholar
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Registered: ‎08-01-2012

7.5 hours is waaaay too long. I can do a fast elaboration (RTL only, black box all IPS) of our design (nearly fully ultrascale) in two minutes, and that includes creating the project and adding all the sources (this is all tcl scripted). Full synthesis with generated IPs takes <20 mins.

If you are re-using ASIC code, I suspect you have RAMs that are not mapping nicely to Xilinx BRAMs. this is usually what kills elaboration times as it has to build large rams from logic.

Maybe you should look through the warnings and check if you have warnings about things not mapping to ram properly. 

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