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nadaumtimuj
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Registered: ‎01-29-2021

AirHDL register array import in VIVADO

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I am using AirHDL to import IP to my vivado design. I am getting VHDL files from AirHDL. For a single register, it works fine on my project. But when I create a register array in AirHDL and then import it into my project, I receive the following error:

Port type 'slv32_array_t' is not recognized. Only std_logic and std_logic_vector types are allowed for ports. See the documentation for more details

Any solution? Thanks.

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richardhead
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Registered: ‎08-01-2012

What are you trying to import it to? If you import the HDL as is, then you shouldnt have a proble, assuming you have slv32_array_t in a package somewhere. But if its as a block design then you need to remember you can only use basic types in the block design connections (std_logic, std_logic_vector and integer is about all that works).

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richardhead
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184 Views
Registered: ‎08-01-2012

What are you trying to import it to? If you import the HDL as is, then you shouldnt have a proble, assuming you have slv32_array_t in a package somewhere. But if its as a block design then you need to remember you can only use basic types in the block design connections (std_logic, std_logic_vector and integer is about all that works).

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nadaumtimuj
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Registered: ‎01-29-2021

Yes, it is a block design. The AirHDL support team helped me to flatten the array in a wrapper which worked. Thanks.

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