I am trying to route a signal to two output ports (e.g. signal_out1 <= signal, signal_out2 <= signal, where signal_out# is an output port). The design seems to synthesizefine, but I run into problems translating. When translating, the tool reads my UCF file and it says one of the output ports (signal_out#, one or the other) is not found. When I looked at the technology schematic I noticed that one of the signal_out# was connected to an OBUF, and the other was an 'alias' of the first signal.
Is there a way to tell the synthesis not to create 'aliases'? I've looked around but can't seem to find anything that I understand.