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brianm25
Newbie
Newbie
4,461 Views
Registered: ‎02-19-2009

'Alias' problem

Hello,

 

I am trying to route a signal to two output ports (e.g. signal_out1 <= signal, signal_out2 <= signal, where signal_out# is an output port). The design seems to synthesizefine, but I run into problems translating. When translating, the tool reads my UCF file and it says one of the output ports (signal_out#, one or the other) is not found. When I looked at the technology schematic I noticed that one of the signal_out# was connected to an OBUF, and the other was an 'alias' of the first signal.

 

Is there a way to tell the synthesis not to create 'aliases'? I've looked around but can't seem to find anything that I understand.

 

Any help is appreciated, thanks.

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gszakacs
Instructor
Instructor
4,436 Views
Registered: ‎08-14-2007

You could try using the "KEEP" attribute on the port signals, however as top level

ports I find it strange that synthesis would need this constraint.  Another workaround

would be to instantiate the OBUFs for each port.

-- Gabor
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