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Participant
Participant
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Registered: ‎04-11-2017

Array in VHDL

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Hello Everyone!

 

I have question on synthesis of array type signals.

Suppose I have an signal "SS"which is a array of  size 12 of type std_logic_vector(7 downto 0).

now I assign each element of array in different IF ELSE loop as below:

 

example:

process(clk)

variable i : integer:=0;

begin

if(rising_edge(clk))then

if(......)then

  SS(i) <= x"44";

i := I + 1;

elsif(.....)then

 SS(i) <= x"55";

i:= i + 1;

elsif(.....)then

  SS(i) <= x"78";

........

 

 

Question: Does the synthesis infer latches for signal "SS" as i am not assigning every element in every if-else condition?

 

 

 

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Visitor
Visitor
3,507 Views
Registered: ‎02-08-2017

It would infer registers for each of the array elements, not latches, since you are in a clocked process.  The fact that it is an array is a convenience for you syntactically, but is irrelevant to the tool.  It would do the same thing with 12 independently declared signals, where each signal was set according to an index counter in sequence.   

 

It is often instructive to write up a quick test and then elaborate and/or synthesize it in Vivado and view the available schematics to see what is really produced.  The elaborated schematic provides a higher level view and the synthesis schematic provides a more detailed hardware specific view.  Both are nice to use from time to time to sanity check your HDL.

 

Scott

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Visitor
Visitor
3,508 Views
Registered: ‎02-08-2017

It would infer registers for each of the array elements, not latches, since you are in a clocked process.  The fact that it is an array is a convenience for you syntactically, but is irrelevant to the tool.  It would do the same thing with 12 independently declared signals, where each signal was set according to an index counter in sequence.   

 

It is often instructive to write up a quick test and then elaborate and/or synthesize it in Vivado and view the available schematics to see what is really produced.  The elaborated schematic provides a higher level view and the synthesis schematic provides a more detailed hardware specific view.  Both are nice to use from time to time to sanity check your HDL.

 

Scott

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Moderator
Moderator
2,755 Views
Registered: ‎09-15-2016

Hi @mayflowers4972,

 

Also, vivado synthesis should issue a warning for the instance in message. For example like: [Synth x-123] inferring latch for variable 'abc'.

 

Something like this should infer latch with if:

 

process(clr, d, g)
begin
if (clr = '1') then
q <= '0';
elsif (g = '1') then
q <= d;
end if;

 

where g,d,clr are inputs and q is output (std_logic).


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Participant
Participant
2,692 Views
Registered: ‎04-11-2017
Thank You Friend for your Answer!
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Participant
Participant
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Registered: ‎04-11-2017
Thank you dear Friend!.. Your explanation made my understanding very much better. As You said it is a ggod practice to first write a small code and do synthesize to clarify the doubts.
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