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Registered: ‎06-04-2020

Artix 7 useable pins

Hi,

Sorry if this has been asked before but didn't find any results for it.

We are using the Artix xc7a100tftg256-1. We also used the Mentor block for this fpga on our schematic. The pins were assigned based on the Mentor block and not the Vivado tool.  This page (https://www.xilinx.com/support/packagefiles/a7packages/xc7a100tftg256pkg.txt) seems to correlate with the Mentor block.The Vivado tool (from the constraint file) is stating that some pins are not valid for use.

My assumption is that Vivado is correct, and Mentor and the "link" are not. 

My question is: which one is correct? Also, for the future reference where is the accurate resources? I did try to find this info from Xilinx datasheets but I was lost. I am not usually a fpga developers so most of this is foreign to me.

Thx in advance,

Rob

 

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Registered: ‎01-22-2015

@zorroslade000 

Welcome!

For pinout information on 7-Series FPGAs (like your Artix-7), I consider the Xilinx document, UG475, and package files (like the one you have referenced) to be the most accurate and up-to-date information.

You say:
The Vivado tool (from the constraint file) is stating that some pins are not valid for use.

Please be more specific. 

  1. What do you mean by "the constraint file"?   
  2. Can you give us an example that shows disagreement between Vivado and the package file?

Cheers,
Mark

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Registered: ‎06-04-2020

Hi,

My constrain file is at the end (xdc).

I get this error, [DRC UCIO-1]. Problem ports are rmii_rtl_0_txd[1:0] (H13, H12), rmii_rtl_0_rx_er (J16), GPIO_0_tri_io[4] (F12), and reset_rtl_0 (G12).

Package PinBankPackage Pin TypeMentor Name
H13BanklessGNDIO_L20N_T3_A19_15
H12BanklessVCCAUXIO_L20P_T3_A20_15
J16BanklessGNDIO_L23N_T3_FWE_B_15
F12BanklessVCCAUXIO_L16P_T2_A28_15
G12BanklessGNDIO_L19N_T3_A21_VREF_15

 

Well, "Package Pins" (in the "Window" menu) in Vivado correlates with UG475 and not the "link" and Mentor's block. Am I reading this wrong?

# *************************************************************************************

# *** Configuration Voltage and Configuration Banks Voltage Select ***
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]

# sys clock
create_clock -period 20.345 -name CLK -add [get_ports {CLK}];
set_property PACKAGE_PIN D13 [get_ports {CLK}];
set_property IOSTANDARD LVCMOS33 [get_ports {CLK}];


set_property PACKAGE_PIN P5 [get_ports {USB_UART_txd}]; # USB TXD
set_property IOSTANDARD LVCMOS33 [get_ports {USB_UART_txd}];
set_property PACKAGE_PIN M6 [get_ports {USB_UART_rxd}]; # USB RXD
set_property IOSTANDARD LVCMOS33 [get_ports {USB_UART_rxd}];

# *** I/O pin standards ***
set_property PACKAGE_PIN B9 [get_ports {GPIO_0_tri_io[0]}];
set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_0_tri_io[0]}];
set_property PACKAGE_PIN D8 [get_ports {GPIO_0_tri_io[1]}];
set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_0_tri_io[1]}];
set_property PACKAGE_PIN C16 [get_ports {GPIO_0_tri_io[2]}];
set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_0_tri_io[2]}];
set_property PACKAGE_PIN D15 [get_ports {GPIO_0_tri_io[3]}];
set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_0_tri_io[3]}];
set_property PACKAGE_PIN F12 [get_ports {GPIO_0_tri_io[4]}];
set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_0_tri_io[4]}];
set_property PACKAGE_PIN F13 [get_ports {GPIO_0_tri_io[5]}];
set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_0_tri_io[5]}];
set_property PACKAGE_PIN E16 [get_ports {GPIO_0_tri_io[6]}];
set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_0_tri_io[6]}];

set_property PACKAGE_PIN G12 [get_ports {reset_rtl_0}];
set_property IOSTANDARD LVCMOS33 [get_ports {reset_rtl_0}];

# not sure why are needed
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets CLK50M_IBUF];
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets CLK_IBUF];
#set_property SEVERITY {Warning} [get_drc_checks UCIO-1]

# phy X700 - log phy
create_clock -period 20.000 -name CLK50M -add [get_ports {CLK50M}];
set_property PACKAGE_PIN N14 [get_ports {CLK50M}]; # ext 50 MHz
set_property IOSTANDARD LVCMOS33 [get_ports {CLK50M}];
set_property PACKAGE_PIN F15 [get_ports {reset_rtl_0}]; # ext reset from phy
set_property IOSTANDARD LVCMOS33 [get_ports {reset_rtl_0}];
set_property PACKAGE_PIN A14 [get_ports {MDIO_0_mdio_io}]; # config data
set_property IOSTANDARD LVCMOS33 [get_ports {MDIO_0_mdio_io}];
set_property PACKAGE_PIN B16 [get_ports {MDIO_0_mdc}]; # config clk
set_property IOSTANDARD LVCMOS33 [get_ports {MDIO_0_mdc}];

set_property PACKAGE_PIN B14 [get_ports {rmii_rtl_0_tx_en}]; # trans en
set_property IOSTANDARD LVCMOS33 [get_ports {rmii_rtl_0_tx_en}];
set_property PACKAGE_PIN H12 [get_ports {rmii_rtl_0_txd[0]}]; # tx 0
set_property IOSTANDARD LVCMOS33 [get_ports {rmii_rtl_0_txd[0]}];
set_property PACKAGE_PIN H13 [get_ports {rmii_rtl_0_txd[1]}]; # tx 1
set_property IOSTANDARD LVCMOS33 [get_ports {rmii_rtl_0_txd[1]}];
set_property PACKAGE_PIN H14 [get_ports {rmii_rtl_0_crs_dv}]; # crs dv
set_property IOSTANDARD LVCMOS33 [get_ports {rmii_rtl_0_crs_dv}];
set_property PACKAGE_PIN G16 [get_ports {rmii_rtl_0_rxd[0]}]; # rx 0
set_property IOSTANDARD LVCMOS33 [get_ports {rmii_rtl_0_rxd[0]}];
set_property PACKAGE_PIN J15 [get_ports {rmii_rtl_0_rxd[1]}]; # rx 1
set_property IOSTANDARD LVCMOS33 [get_ports {rmii_rtl_0_rxd[1]}];
set_property PACKAGE_PIN J16 [get_ports {rmii_rtl_0_rx_er}]; # rx err
set_property IOSTANDARD LVCMOS33 [get_ports {rmii_rtl_0_rx_er}];

Rob

 

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Registered: ‎01-22-2015

@zorroslade000 

For the xc7a100tftg256-1 package pins you have shown, I find complete agreement between:

  • Vivado v2018.3 "Package Pins" window 
  • package file found in link you provided
  • Mentor name

That is, all three show:

Pin   Pin Name                  Memory Byte Group    Bank    VCCAUX Group    Super Logic Region    I/O Type 
H13   IO_L20N_T3_A19_15         3                    15      NA              NA                    HR     
H12   IO_L20P_T3_A20_15         3                    15      NA              NA                    HR     
J16   IO_L23N_T3_FWE_B_15       3                    15      NA              NA                    HR     
F12   IO_L16P_T2_A28_15         2                    15      NA              NA                    HR      
G12   IO_L19N_T3_A21_VREF_15    3                    15      NA              NA                    HR    


Where are you getting the words "Bankless",  "GND", and "VCCAUX" in the table you have shown?

Also, "error, [DRC UCIO-1]", indicates a problem with the xdc-file constraints that you have written.    Please tell me what the pins in question are being used for - an IP interface?

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Registered: ‎06-04-2020

Hi,

Thanks for the response. In Vivado on the menu, "Window" -> "Package Pins". You have to be in Implementation. In the window, you can search for your pins.

Rob

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Registered: ‎06-04-2020

Hi,

I am trying to use the microblaze _> axi_ethernetlite -> mii_to_rmii, and having lots of problems with pins.

Rob

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Registered: ‎01-22-2015

Rob,

This is a strange problem and sounds "bug like".

I'm quite sure this is not a problem with documentation nor with Vivado's understanding of the pinout for the Artix-7.

Instead, something about microblaze/IP is causing your xdc files constraints to be ignored/changed.  I have seen this before in the following post:
https://forums.xilinx.com/t5/Implementation/ERROR-DRC-UCIO-1-Unconstrained-Logical-Port-during-bitstream/m-p/1022513#M26208

You may find a solution by searching the Forum more for the error, DRC-UCIO-1.  If you can't find a solution, then I would start a new thread on the Forum with a title something like "Error DRC-UCIO-1 with microblaze and ethernetlite".

Good luck,
Mark

 

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Registered: ‎06-04-2020

Thx. Sorry, I was out on vaca. I am going to talk to the FAE, but I tried a few things and wanted to doc them somewhere.

I upgraded my project from 2018.3 version to 2019.2 and that didn't workl

I recreated my schematic and that didn't work.

I decided to verify the conflicting pins with a axi gpio. It did allow the conflicting pins to be used. I need to talk to the FAE as for why. I think that the axi ethernetlite expects the the ddr module to be used. If this is the case, i would have expected a diff error.

Rob

 

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