Assignment under multiple single edges is not supported for synthesis

[gsatyamohanraju]

Hi

I recently got a new Virtex-6 (ML605) board with ISE 11.3ver tool set.

I am doing basic testing to get used to it. 

Here is my code snipp:

module counter(Q, clk_l, rst);
   input    clk_l, rst;       
   output reg  [3:0] Q = 4'h0;
   
  always @ (posedge(clk_l) or posedge(rst)) begin  
   Q <= Q + 4'h1; // increment
   if(rst == 1'b1) // reset
     begin
      Q <= 4'h0;   
    end
   end

endmodule

When I synthesis my code I get following warnings,

WARNING:HDLCompiler:1128 - : Assignment under multiple single edges is not supported for synthesis
WARNING:Xst:647 - Input <clk_l> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Also my code does not function on the virtex-6 FPGA.

Previously this code is testing on Spartan-3E FPGA with ISE 9.2 ver ans it worked properly.

Also when I modify  "always @ (posedge(clk_l) or posedge(rst))" to "always @ (posedge(clk_l) )" it works on Virtex-6 with ISE 11.3ver.

Can anyone tell what might be the reason for this?

- Raju

[gszakacs]

Synthesis generally uses templates to find known items like flip-flops

with asynchronous reset.  If you deviate enough from the template,

even though the code is equivalent it often fails to map your logic into

the proper flip-flop element.  I would suggest using the standard form

placing the reset term first and the clocked portion in the else like:

reg [3:0] foo;

always @ (posedge clk or posedge rst)

if (rst)

  foo <= 0;

else

  foo <= foo + 1;

While this is equivalent to:

always @ (posedge clk or posedge rst)

begin

  foo <= foo + 1;

  if (rst) foo <= 0;

end

the synthesis tool may have a hard time recognizing it.

When in doubt you can look in the language templates (light bulb icon in the ISE GUI)

to find the most reliable coding to generate the flip-flop or other structure you want.

By the way I have found that the synthesis tool also has a problem with

logic in the reset term like:

always @ (posedge clk or posedge (a | b))

if (a | b)

 . . .

equivalent to

wire c;

assign c = a | b;

always @ (posedge clk or posedge c)

if (c)

 . . .

The latter works in synthesis, the former does not.

HTH,

Gabor

[gsatyamohanraju]

Hi Gabor. Thanks for the info.

When I synthisis my original code in ISE 11.3 and try to "create Timing Constarinats" it says "Design has no clock". And the code does'nt function on Virtex 6.

I am puzzled here because the same code worked in ISE 9.2 for Spartan 3E.

Is there any changes in coding standerds from ISE 9.2/Spartan3E to ISE 11.3/Virtes6 ?

Any help on this will be very helpful to me as many of my previous designs that worked in Spartan 3E are not working on Virtex 6.

- Raju

[gsatyamohanraju]

Additional info.

I tried even  with,

(* clock_signal = "yes" *)    input    clk; 

- Raju

[gszakacs]

This is really starting to sound like a typical messed-up project file

bug.  Did you start a new project with the  new ISE version tools,

or did you just open the original 9.2 project and upgrade it, make

changes, etc.?  I would suggest making a new project to see

if the problem persists.  If your project has a lot of files in it

you could also try to use the .restore file to recreate the project

file.  The instructions for this are in the project_name.restore

file which you can open with any text editor.

Regards,

Gabor

[gsatyamohanraju]

The project has been build in ISE 11.3, from the original source files. Absolutly no project files of ISE 9.

- Raju

[eilert]

Hi,

XILINX has written new HDL-Parsers for the S6/V6 families. (at least for VHDL, but when I read this probably for verilog too)

So the synthesis rules may have changed with that.

Actually, I never understood thew reason why asynchronous resets in verilog are triggered with the posedge statement.

Something like

always @ (posedge(clk_l) or rst) begin

would be much more logical to me, (with my VHDL view of things).

Is that line legal verilog?

Just for completeness:

Has there be a recent change in the languange reference about this topic? 

Or is it just a bug? (Other verilog users should have observed it too then.)

Have a nice synthesis

  Eilert

[gsatyamohanraju]

Thanks Eilert.

So may be its the new parser.Think this new parser has some strict rules thatn its older version.

Hope to hear from other Virtex/ISE11.3 users.

Regards

Raju