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sylviaelse
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Registered: ‎02-23-2019

Asynchronous logic

If I have an expression such as !(a & b & c), then its output should be 1 as long as any of the three inputs is zero even if the other inputs are changing. Yet I cannot convince myself that this would be the case if this expression is implemented using a LUT. To get the 1 output the LUT has to select an element from its table that contains 1. But if the other two inputs are changing, there seems no guarantee that the LUT will select any element at all, and the output would presumably be zero by default. Or perhaps it's 1 by default, and some other expression would break.

This situation arises for me in the context of startup with a PLL producing output for one clock domain, and DDR3 memory running in a different clock domain doing its calibration. Just ANDing various signals together and synchronizing them looks to me as if it could still fail. Yet I'm loath to waste resources on synchronizing them separately, and then ANDing them if I'm just mistaken about this hazard.

Any thoughts on this? A reference to relevant documentation would be great. I've looked, but not found.

Sylvia.

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drjohnsmith
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Registered: ‎07-09-2009

What's you level of experience, I'm guessing new to logic design, possibly at college. If I'm wrong apologies. 

A LUT does no selection,

Its simply a "PROM" look up table, with a number of inputs and one output,
so if you have 4 inputs, then the Look Up Table contains 16 entrees, one for each of the possible inputs, and once programmed by your code, outputs the 1 or 0 your design has.

The "answer" to this sort of problem, which I'm guessing you have not done is to do a quick simulation.

As you progress in logic design, you will spend most of your time in simulation, so now is the time to learn the basics.


Re the wider question,
in all logic, if the inputs to a function change, the outputs change,
if the inputs are not synchronous to each other, and the output is not sampled synchronously, then you will see glitches.

this is called crossing clock domains.

Its up to your system design to mitigate the cross clock domain problems,
there are very many ways to do this

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avrumw
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Registered: ‎01-23-2009

The Xilinx literature is unclear here. At no point does the documentation state that the LUT is glitch free - if you are switching from one combination of inputs that produces an output (say 0) to another combination that produces the same output, there is no guarantee that there isn't a transient glitch to a 1 as the inputs are switching.

That being said, it is also not stated that they are not glitch free - at least in more restricted situations. For example if you have an input combination that produces a 0, you switch to a different input situation that also produces 0 that is one Hamming distance away (i.e. only one input bit is changing) is there a chance that the signal will glitch to a 1? I don't know - it certainly isn't stated in any documentation.

Maybe @lowearthorbit might be able to provide some insight (I think he has talked about this in the past).

Avrum

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drjohnsmith
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Registered: ‎07-09-2009

My penny's worth on the question are LUTs glitch free,

Even if LUTs are inherently glitch free,
all they do is produce an output based upon the input,

the input logic to them can not be timed to be identical,

so you cannot guarantee the output till all inputs have propagated through,

QED, the resultant is the output of a LUT can be a glitch.
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sylviaelse
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Registered: ‎02-23-2019

Thanks.

After further considering the likely implementations of a LUT, I'm rather suspecting that they're not glitch free even in the simple case of one input changing where the eventual output won't change. This means that a simple case such as selecting from a pair of asynchronous inputs won't work

muxab = (asel & a) | (bsel & b)

even if the synthesizer is forced to use three LUTs for this.

Xlinix could usefully comment on this, with particular reference to whether the same issue applies to a MUXF7 or similar.

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drjohnsmith
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Registered: ‎07-09-2009

IMHO,

I don't think Xilinx need to comment on this,

All asynchronous logic , by definition WILL have the capacity to glitch during the period of the propagation through the logic.

After the propagation time, the output will be static.

Its inherent in the asynchronous part of the definition.

it up to the designer to know this and design accordingly.

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sylviaelse
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Registered: ‎02-23-2019

What kind of NAND gate generates anything but one on its output when at least one input is zero, regardless of what the other inputs are, including while they are changing from one state to the other?

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drjohnsmith
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Registered: ‎07-09-2009

Ok @sylviaelse
lets call this quits,

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