08-23-2017 04:11 PM
WARNING:NgdBuild:483 - Attribute "INIT" on
"I0/I1/I2/I11/U0/blk00000003/sig000000aa" is on the wrong type of object.
Please see the Constraints Guide for more information on this attribute.
The element is a CoreGen Divider cg3
Is this a problem or is it something that I can ignore?
I searched the boards and found an instance of the same issue showing up a few years associated with a different problem and was asked to be moved to its own thread. Appears to not have been re-submitted.
08-23-2017 06:46 PM
08-23-2017 07:13 PM
08-25-2017 12:06 AM - edited 08-25-2017 12:07 AM
08-25-2017 08:29 AM
This is the CoreGen Macro that was generated using ISE14.7 The specific LUT/ logic set is listed in the subject line. The warning is from an INIT either placed on the buffer driving sig0000000aa or is from the INIT on the Flop that receives that signal. can't tell which. The specific ISE build warning is listed in the thread
08-25-2017 08:33 AM
08-27-2017 10:49 AM
This is actually the mismatch between type of INIT - which is std_logic_vector - and the type of your signal - in this case is std_logic.
architecture STRUCTURE of div_u24d12_cg3 is signal blk00000003_sig000000aa : STD_LOGIC; .... .... .... begin .... .... blk00000003_blk0000077f : LUT1 generic map( INIT => X"1" ) port map ( I0 => blk00000003_sig000006e9, O => blk00000003_sig000000aa ); .... .... .... end STRUCTURE;
You don't need to be worry about it. Go ahead with your code development. This happens so many times in Xilinx cores and seems that they don't intend to fix such bugs :-)
Happy HDL coding ;-)
08-28-2017 01:31 PM
Thank you! I couldn't see the forest for the tree's thought it was something simple but makes sense and I really don't care about the initial conditions in this application. It is all cleared with valid calculations prior to use.