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rbonella
Observer
Observer
2,756 Views
Registered: ‎07-18-2017

Attribute "INIT" on "I0/I1/I2/I11/U0/blk00000003/sig000000aa" is on the wrong type of object

WARNING:NgdBuild:483 - Attribute "INIT" on
"I0/I1/I2/I11/U0/blk00000003/sig000000aa" is on the wrong type of object.
Please see the Constraints Guide for more information on this attribute.

 

The element is a CoreGen Divider cg3

Spartan6

ISE14.7

 

divider_u24d12_cg3.vhd

 

Is this a problem or is it something that I can ignore?

I searched the boards and found an instance of the same issue showing up a few years associated with a different problem and was asked to be moved to its own thread. Appears to not have been re-submitted.

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7 Replies
rbonella
Observer
Observer
2,733 Views
Registered: ‎07-18-2017

Some Additional Information:

Release 14.7 ngdbuild P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.

Command Line: C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe
-intstyle ise -dd _ngo -sd ../../vhdl -nt timestamp -uc
.../vhdl/rf_top.ucf -p
xc6slx9-tqg144-3 rf_top.ngc rf_top.ngd
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rbonella
Observer
Observer
2,724 Views
Registered: ‎07-18-2017

The controller is in a class 3 medical device. I need to disposition this warning and or get the problem fixed. As it is in the CoreGen Macro Xilinx would need to fix it and I don't see any way to flag this as a bug to Xilinx other than positing in this forum.

The Divider was simulated extensively, both by itself and in a Unit Test with significant other logic. Vectors were captured from an operating system and played back and compared to captured output vectors and against simulation outputs with 100% match so it appears to be ok.
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embedded
Advisor
Advisor
2,635 Views
Registered: ‎06-09-2011

@rbonella,

Would you please specify on which primitive you get such warning/error message?

What is that HDL file you mentioned? Is it possible to upload the file?

 

Hossein

Thanks,
Hossein
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rbonella
Observer
Observer
2,616 Views
Registered: ‎07-18-2017

This is the CoreGen Macro that was generated using ISE14.7  The specific LUT/ logic set is listed in the subject line. The warning is from an INIT either placed on the buffer driving sig0000000aa or is from the INIT on the Flop that receives that signal. can't tell which. The specific ISE build warning is listed in the thread

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rbonella
Observer
Observer
2,613 Views
Registered: ‎07-18-2017

If I had to guess the INIT on the buffer term is what threw the warning in which case I really don't care. Just trying to make sure that there isn't something broken with the VHDL for synthesis.
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embedded
Advisor
Advisor
2,477 Views
Registered: ‎06-09-2011

@rbonella,

This is actually the mismatch between type of INIT - which is std_logic_vector - and the type of your signal - in this case is std_logic.

architecture STRUCTURE of div_u24d12_cg3 is
  signal blk00000003_sig000000aa : STD_LOGIC; 
....
....
....
begin
....
....

  blk00000003_blk0000077f : LUT1
    generic map(
      INIT => X"1"
    )
    port map (
      I0 => blk00000003_sig000006e9,
      O => blk00000003_sig000000aa
    );
....
....
....

end STRUCTURE;

You don't need to be worry about it. Go ahead with your code development. This happens so many times in Xilinx cores and seems that they don't intend to fix such bugs :-)

 

Happy HDL coding ;-)

Hossein

Thanks,
Hossein
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rbonella
Observer
Observer
2,428 Views
Registered: ‎07-18-2017

Hi Hossein,

Thank you!  I couldn't see the forest for the tree's thought it was something simple but makes sense and I really don't care about the initial conditions in this application. It is all cleared with valid calculations prior to use. 

 

Randy...

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