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410 Views
Registered: ‎07-18-2018

Auto-hierarchy (srcscanner) can't handle IP block instantiation based on top-level SV parameter defined in project settings

See the following code (System Verilog). myaddsub is an adder/subtractor Xilinx IP block, but it could be any other IP block. The project consists of these 2 modules and the IP block. The problems with it are as follows (using Vivado 2018.2):

 

1. if I set PARAM in project settings to AND, hierarchy is displayed correctly and synthesis works

2. if I set PARAM in project settings to SUM, hierarchy is not displayed correctly (myaddsub shows as being outside the hierarchy) and synthesis fails saying that myaddsub is missing

3. If I set PARAM in project settings to "SUM", hierarchy is displayed correctly, but synthesis obviously fails with the error message that param is set to "SUM", not SUM or AND.

 

I.e., looks like srcscanner doesn't handle project-defined string parameters correctly. Using an integer parameter instead of a string works fine. Zipped-up project is attached. 

 

--------------------------------

module submod_and
(
input logic [14:0] a,
input logic [14:0] b,
output logic [14:0] c
);

assign c = a & b;

endmodule

 

--------------------------------

 

 

module top
#(
  PARAM
)
(
  input logic clk,
  input logic [14:0] a,
  input logic [14:0] b,
  output logic [14:0] c
);

 

generate
 if (PARAM == "SUM")
 begin
   myaddsub u (
     .A (a),
     .B (b),
     .CLK (clk),
     .CE (1),
     .S (c)
 );
 end else if (PARAM == "AND")
 begin
   submod_and u
   (
     .a(a),
     .b(b),
     .c(c)
   );
  end else
    $error("Param must be either SUM or AND, not %s", PARAM);

endgenerate

endmodule

 

--------------------------------

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1 Reply
Moderator
Moderator
329 Views
Registered: ‎05-31-2017

Re: Auto-hierarchy (srcscanner) can't handle IP block instantiation based on top-level SV parameter defined in project settings

Hi madelman@tower-research.com,

 

Thanks for sharing the project reproducing the issue. I have checked this in Vivado 2018.2 and I have observed the scenario that you have reported. I have later checked the same project in Vivado 2018.3 (Internal build) and it seems that the issue has been fixed and works correctly when setting the parameter value from project settings.

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