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nskabra
Adventurer
Adventurer
8,102 Views
Registered: ‎02-10-2015

BRAM inference is not correct - want to use asynchronous read

I have a behavioral code of single port memory.

 

The output of the memory (ie. read_data_out) is unregistered that means I want read_data immediately after address is changed (no dealy at all)

 

For this code Vivado implements memory in LUTs

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avrumw
Expert
Expert
8,091 Views
Registered: ‎01-23-2009

I answered this question in your previous thread. Block RAMs have synchronous reads, and therefore cannot be inferred for asynchrounous reads. Period.

 

The only RAMs that can perform asynchronous reads are LUT RAMs (and obviously flip-flops).

 

You will need to find a way to make your application work with synchonous reads if you want to use a BRAM. One "trick" that can work in some applications is to use the negative edge of the clock to clock the BRAM. This way, if your address comes from a flip-flop (on the rising edge), the RAM is read on the falling edge, and the data can be available on the next rising edge; from the point of view of the system, this looks like an asynchronous read. Of course, this only works at "slower" speeds, since you only get 1/2 clock period for address setup and 1/2 clock period for the RAM clock-to-Q to meet the setup of the capture flip-flop.

 

Avrum

m@c2018
Visitor
Visitor
566 Views
Registered: ‎10-21-2018

In my case, using the negative edge in the vhdl code, it caused Vivado to insert an inverter into the Bram clock input, so when the positive clock edge arrives, the propagation time of the inverter is enough for Bram to see the negative edge, so, the time left for access is the clock period minus the propagation time of the inverter, practically the entire cycle! My project works fine!

Many thanks Avrum!

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