Vivado can correctly infer READ_FIRST memory with byte selectable write enable signals
architecture rtl of RAM_single_port is
subtype memory_cell_type is std_logic_vector(8 * width_in_bytes - 1 downto 0);
type ram_chip_type is array (0 to depth - 1) of memory_cell_type;
begin
portA: process is
variable ram : ram_chip_type;
begin
wait until rising_edge(clk);
-- read
douta <= ram(addra);
-- write
for i in 0 to width_in_bytes - 1 loop
if wea(i) = '1' then
ram(addra)(8 * i + 7 downto 8 * i) := dina(8 * i + 7 downto 8 * i);
end if;
end loop;
end process;
end architecture;
but if the logic is changed slightly to WRITE_FIRST
portA: process is
variable ram : ram_chip_type;
begin
wait until rising_edge(clk);
-- write
for i in 0 to width_in_bytes - 1 loop
if wea(i) = '1' then
ram(addra)(8 * i + 7 downto 8 * i) := dina(8 * i + 7 downto 8 * i);
end if;
end loop;
-- read
douta <= ram(addra);
end process;
Vivado can no longer infer the RAM, and reports
[Synth 8-2914] Unsupported RAM template
Yet WRITE_FIRST with byte selectable write enable signals is a supported RAM type within the IP library
