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aaron_holliday
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Registered: ‎01-26-2017

BRAM optimised completely out of design

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Hi,

 

I have probably what is a common question: Besides data path being incorrect, what are some of the causes of synthesis to optimise BRAMs away? I am reasonably sure that my inputs and outputs are correct for my BRAMs in my design, and in simulation the BRAMs are being read from and written to. Now, as I understand it, simulation of the RTL will not include any resource optimsations, so there is no guarantee that working in simulation demonstrates that the design works in implementation. However, if it is working in simulation, the datapath is likely correct. 

 

Can other things affect BRAM? I am considering that incorrect timing constraints is messing with synthesis. If the BRAMs are being driven by clocks that are incorrectly constrained, will this cause the BRAMs to be synthesised out? But I assumed timing constraints affected implementation only...

 

I might add that each of my BRAMs submodule runs synthesise BRAM usage fine, but it is only when the synth run finishes entirely that BRAM usage is listed as 0.0

 

Thanks for your time

--- Estimated Development time: 2*Pi*(planned completion date) ---
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viviany
Xilinx Employee
Xilinx Employee
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Registered: ‎05-14-2008

The utilization in Synthesis report does not include the out-of-context IPs/modules. This is because the Synthesis process does not look into those out-of-context modules as they're already synthesized.

See this Answer Record for details:https://www.xilinx.com/support/answers/59282.html

 

-vivian

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hongh
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Registered: ‎11-04-2010
Hi, @aaron_holliday ,
If the output of BRAM are not finally used by the FPGA port, the BRAM will also be optimized away.
You can try to probe the output pins of BRAM to FPGA port and check whether the BRAM will still be optimized away.
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aaron_holliday
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Registered: ‎01-26-2017

hi @hongh,

 

Currently most of the BRAMs feed a display buffer BRAM which then leads to HDMI output pins (i.e some BRAM outputs go directly to FPGA output ports). I understand that if the BRAMs were outputting to signals only, they would be optimised away for sure.

 

Some of my BRAM addresses use the attribute MARK_DEBUG, which I believe should prevent optimisation from occurring. I have also run a synthesis with DONT_TOUCH applied to the BRAMs but still they are optimised away.

 

 

--- Estimated Development time: 2*Pi*(planned completion date) ---
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avrumw
Expert
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Registered: ‎01-23-2009

If the BRAMs are being optimized away, there is something fairly grossly wrong with your design. The problem has to be functional - something like

  - the BRAM is held in reset all the time

  - the BRAM clock is tied to a constant

  - the BRAM inputs are being tied to a constant

     - this can be as little as one input - like the ENA and/or WEA

  - the BRAM outputs are not being used

     - the "break" can be as close as the direct output of the RAM all the way to the outputs of the design

  - (there may be others that I can't think of)...

 

All of these should be fairly obvious in a simulation - your simulation shouldn't work if any of these are true.

 

Constraints cannot affect whether some part of the logic is optimized out or not - even if you have no constraints (which, of course, cause all kinds of other problems) this will not affect whether the BRAM is optimized out or not.

 

A MARK_DEBUG or a DONT_TOUCH ultimately won't keep a cell that has no use - the FPGA will not leave things dangling (even if you tell it to).

 

Considering that you say the RAM is being both written and read (in simulation), the problem probably exists "further down" - some module between the BRAM and the ultimate outputs are doing something that makes the outputs of the RAM irrelevant. For example, if you "AND" the outputs of the RAM with 0, then the outputs become irrelevant, and the RAM will be optimized out.

 

Avrum

anusheel
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Registered: ‎07-21-2014

@aaron_holliday

 

Also, can you please check whether the BRAM was optimized in Synthesis phase or in opt_design(logical optimization of Implementation)?

 

Thanks

Anusheel 

aaron_holliday
Adventurer
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Registered: ‎01-26-2017

@avrumw@anusheel

 

Hey guys,

 

It turns out that the BRAMs were not being optimised out at all. Because my BRAMs were out-of-context, I think they were not showing up in synthesis report, however after opening synthesised design, and using the report_utilization command, I can see that my BRAM usage is at around 40%. 

 

Thanks for taking the time to help out

 

 

--- Estimated Development time: 2*Pi*(planned completion date) ---
viviany
Xilinx Employee
Xilinx Employee
2,392 Views
Registered: ‎05-14-2008

The utilization in Synthesis report does not include the out-of-context IPs/modules. This is because the Synthesis process does not look into those out-of-context modules as they're already synthesized.

See this Answer Record for details:https://www.xilinx.com/support/answers/59282.html

 

-vivian

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Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
-------------------------------------------------------------------------------------------------

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