04-27-2015 05:15 AM
04-27-2015 07:00 AM
04-28-2015 09:33 AM
06-19-2015 12:29 AM
07-01-2015 01:52 PM
You're instantiating your "ram" module 33 times, and each one infers a single 1Kx8 memory, so that's how you end up with 33 copies of RAMB18. The tools might not be smart enough to reliably (or ever) merge inferred RAMs across modules, even though it's perfectly obvious you could pack two 1Kx8 into a single RAMB18.
The solution is to rewrite or replace your "ram" module so it implements multiple byte lanes inside. UG901 (Vivado Synthesis) has this link to a ZIP file full of inference examples for block RAM (and other common cases where you want to reliably infer a particular FPGA resource):
I'd recommend rewriting your wrapper to use one of the byte-write-enable block RAM modules in here. It looks like you should probably use a read-first mode module, but I'd review carefully to be sure.