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nhenri
Visitor
Visitor
451 Views
Registered: ‎03-29-2021

BUG: SystemVerilog import scope is not respected

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Hi,

In Vivado, the import scope is not respected, meaning there is conflict between package even if not imported.

Here's an example (code also in attachment):

Screenshot 2021-06-08 162024.jpg

This example declare 2 separate package with a typedef struct of the same name (ts).

The synthesis FAIL because in toto.sv it's use the 'ts' from tata_pkg.sv.

You have to specify the package even if only 'ts' from toto_pkg.sv is visible.

These mean you have to check every package to ensure all name are unique
Is this the behavior wanted or a bug ?

Thank you

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aher
Xilinx Employee
Xilinx Employee
332 Views
Registered: ‎07-21-2014

Hi @nhenri,

Can you please run vivado in single file compilation unit using -sfcu switch in synthesis settings more options

This will scope the declaration only within corresponding file.

 

-Shreyas

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aher
Xilinx Employee
Xilinx Employee
404 Views
Registered: ‎07-21-2014

Hi @nhenri

This looks like an issue in synthesis as only imported packages should be visible in the module. I will follow up on this and keep you posted.

 

Thanks,

Shreyas

----------------------------------------------------------------------------------------------
Try to search answer for your issue in forums or xilinx user guides before you post a new thread.

Kindly note- Please mark the Answer as "Accept as solution" if information provided solves your query.
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aher
Xilinx Employee
Xilinx Employee
333 Views
Registered: ‎07-21-2014

Hi @nhenri,

Can you please run vivado in single file compilation unit using -sfcu switch in synthesis settings more options

This will scope the declaration only within corresponding file.

 

-Shreyas

----------------------------------------------------------------------------------------------
Try to search answer for your issue in forums or xilinx user guides before you post a new thread.

Kindly note- Please mark the Answer as "Accept as solution" if information provided solves your query.
Give Kudos (star provided in right) to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------

View solution in original post

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nhenri
Visitor
Visitor
307 Views
Registered: ‎03-29-2021

Oh thank!

I'm surprise this option is not set by default.

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markcurry
Scholar
Scholar
285 Views
Registered: ‎09-16-2009

Be careful with importing things into the global scope, as you are doing.   My two cents - this is bad form, and pollutes the global name space.  Almost all of the examples in the SystemVerilog spec shows package imports into a specific scope - be it a module, interface, or another package.

By importing into the global scope - especially when using wildcards - one needs to start delving into some rather detailed corners of the spec to fully understand the full scope resolution, and the impact of colliding names.  I'd avoid this mess altogether, unless there were very weird problems you were trying to solve, and you didn't have another method.

Regards,

Mark

nhenri
Visitor
Visitor
274 Views
Registered: ‎03-29-2021

Oh, yes you're right, I didn't realize it.
I mostly do VHDL where you import globally

Note: that if I put the import inside the module toto, I don't see the issue

Screenshot 2021-06-14 110135.jpg

Thank you for your comment !

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