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Scholar
Scholar
774 Views
Registered: ‎08-01-2012

[BUG VIVADO 2019.2] Signed Expression gives warning that unsigned was expected.

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Im confused. I think this is explictly clear that this is a signed expression:

constant c : signed(15 downto 0) := to_signed(-12345, 16);

I think the clue is the fact that it is a signed type and uses the to_signed conversion function (which can take any integer value)

function TO_SIGNED ( ARG: INTEGER; SIZE: NATURAL) return SIGNED;
     -- Result subtype: SIGNED (SIZE-1 downto 0)
     -- Result: Converts an INTEGER to a SIGNED vector of the specified SIZE.

 

But during synthesis you get the following warning for anything that uses a negative literal:

WARNING: [Synth 8-5825] expecting unsigned expression [D:/playarea/signed_warning/signed_warning.vhd:12]

What is Vivado so confused about?

1 Solution

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Scholar
Scholar
266 Views
Registered: ‎08-01-2012

This appears to be fixed in 2020.1

View solution in original post

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Xilinx Employee
Xilinx Employee
755 Views
Registered: ‎02-16-2014

Hi @richardhead 

Tried at my end and looks like this warning comes only in VHDL-2008 mode, in 93 I dont see this warning.

Let me check on this and get back to you.

 

Thanks,

Manusha

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Teacher
Teacher
734 Views
Registered: ‎07-09-2009
@pulim : how about adding it to your regression tests ?
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Scholar
Scholar
506 Views
Registered: ‎08-01-2012

@pulim 

What is the status on this defect?

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Xilinx Employee
Xilinx Employee
458 Views
Registered: ‎02-16-2014

Hi @richardhead 

This is reported and will be fixed in next vivado release.

Thanks,

Manusha

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Scholar
Scholar
267 Views
Registered: ‎08-01-2012

This appears to be fixed in 2020.1

View solution in original post