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Explorer
Explorer
7,627 Views
Registered: ‎12-05-2012

Basic question: Axi single port BRAM READ OPERATION

hello Guys,

 

I am using a single port bram block for both write and read operations (32 bit data).

 

Write operation works perfectly.

But can you tell me what are the signals needed to be sent or changed during rerad operations

 

for example: in write operation

I generate address

I have made my (Write Enable) WE_N to "1111" and also enable signal to '1'

in the same way what are the changes for read operation.??

 

Please help me with this

 

Regards

Pruthvi

 

 

 

 

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34 Replies
Scholar austin
Scholar
7,622 Views
Registered: ‎02-27-2008

Re: Basic question: Axi single port BRAM READ OPERATION

P,

 

There is a wealth of answers to this very basic question online.  HAve you tried to do some research on this yourself?

 

http://www.stanford.edu/class/ee108/bram/bram.htm

Austin Lesea
Principal Engineer
Xilinx San Jose
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Explorer
Explorer
7,617 Views
Registered: ‎12-05-2012

Re: Basic question: Axi single port BRAM READ OPERATION

Hii Austin,

 

I have gone through axi bram controller for single bram port capability I have seen the timing diagrams and tried to follow them

I have asserted the WRITE ENABLE VECTOR zeroes i.e.., ("0000").

made the enable signal constant generated address in vhdl but still cannot read any data .

 

The bram block is connected to bram controller ------> cdma----------> ddr3ram.

the writing works and am not sure which signals need to be asserted for reading operation

 

regards

Pruthvi

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Visitor karimpour
Visitor
7,607 Views
Registered: ‎05-28-2013

Re: Basic question: Axi single port BRAM READ OPERATION

You don't need to do any thing special to read BRAM. The data appear on output port based on the given address.

Try to find some sample HDL source codes on the net.

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Explorer
Explorer
7,603 Views
Registered: ‎12-05-2012

Re: Basic question: Axi single port BRAM READ OPERATION

Thanks for the reply...

 

I think I have problem with the address.

does address means should I send the addresss of BRAM CONTROLLER TO READ DATA FROM it???

 

regards

Pruthvi

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Visitor karimpour
Visitor
7,595 Views
Registered: ‎05-28-2013

Re: Basic question: Axi single port BRAM READ OPERATION

Your question is pretty unclear.

By the way, the best way to learn how a BRAM works is to use Language Templates of ISE for getting an BRAM instance,  to write a simple stimulus for it, and then to simulate it to contemplate its functionality.

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Explorer
Explorer
7,590 Views
Registered: ‎12-05-2012

Re: Basic question: Axi single port BRAM READ OPERATION

Hii,

 

I am working on a zynq Soc module.

 

I HAVE BRAM CONTROLLER CONNECTED TO ZYNQ Processor system.

BRAM BLOCK IS CONNECTED in one end to BRAM controller and other end is made available to connect to VHDL modules.

I can send data from VHDL modules to BRAM BLOCK from there to processor system successfully, but cannot recieve any data which is sent from processor system to BRAM.

 

Are things clear now?

 

Regards

Pruthvi 

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Explorer
Explorer
7,588 Views
Registered: ‎12-05-2012

Re: Basic question: Axi single port BRAM READ OPERATION

This is my basic EDK setup

bram_bus.pngbram_ports.png

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Visitor karimpour
Visitor
7,579 Views
Registered: ‎05-28-2013

Re: Basic question: Axi single port BRAM READ OPERATION

What I recommend is to use EDK wizard to generate your basic modules, and then you can add your application-specific IP into the generated platform. However, you need to have an idea about how you want to interconnect your IP to other parts of the system. For instance, some people use double buffering techniques and so on.

you'd better to take a look at some examples provided by Xilinx, and simulate them to realize how the interconnection protocols work despite the fact there are enough documents related to these concepts.   

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Explorer
Explorer
7,575 Views
Registered: ‎12-05-2012

Re: Basic question: Axi single port BRAM READ OPERATION

I think you are not able to understand my problem.

 

Actually with the current setup, I can send data into BRAM using my VHDL MODULES but I cannot read data out from BRAM . the bram is fed with data from my application in Xilinx SDK.

 

My EDK setup is

 

VHDL MODULE-----> BRAM----> bram controller----> cdma----->AXI hp ports-------> DDR3 RAM (This works good)

when I want to send data in the opposite direction it doesnt work.

 

I have gone through zynq CTT and OCM  cache through BRAM example.

 

If you have any more examples please forward me those links.

 

Can you atleast tell me if my EDK set up is fine as of now to make a read operation ??

Regards

Pruthvi

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Visitor karimpour
Visitor
7,660 Views
Registered: ‎05-28-2013

Re: Basic question: Axi single port BRAM READ OPERATION

Could you specify which data you mean?

1- The data you have just written in BRAM?

2- The data of your DDR3 RAM?

 

Another question? You have written:

"VHDL MODULE-----> BRAM----> bram controller----> cdma----->AXI hp ports-------> DDR3 RAM (This works good)"

Does the whole process, writing data through BRAM , and  ...., into DDR3 RAM, work good? or only writing into BRAM? 

 

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Explorer
Explorer
7,658 Views
Registered: ‎12-05-2012

Re: Basic question: Axi single port BRAM READ OPERATION

The data which I mean I want to read is from the DDR3 RAM.

 

"VHDL MODULE-----> BRAM----> bram controller----> cdma----->AXI hp ports-------> DDR3 RAM (This works good)"

Does the whole process, writing data through BRAM , and  ...., into DDR3 RAM, work good? YES IT WORKS FINE

NOW i WANT TO EXACTLY DO THE REVERSE FLOW ALMOST LIKE A LOOPBACK TEST.

 

Regards

Pruthvi

 

 

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Visitor karimpour
Visitor
7,652 Views
Registered: ‎05-28-2013

Re: Basic question: Axi single port BRAM READ OPERATION

Study the document on the following link carefully and realize how other parts (for example CDMA) work and interact with each other.

When you use EDK, you need to know not only how the modules can be configured but also how they interact with each other. 

http://www.xilinx.com/support/documentation/ip_documentation/axi_cdma/v3_00_a/ds792_axi_cdma.pdf

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Explorer
Explorer
7,649 Views
Registered: ‎12-05-2012

Re: Basic question: Axi single port BRAM READ OPERATION

Thanks for the suggestion but can you tell me what is actually going wrong.

I dont understand only data transfer takes place in only one direction

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Visitor karimpour
Visitor
7,643 Views
Registered: ‎05-28-2013

Re: Basic question: Axi single port BRAM READ OPERATION


@pruthvi_8889 wrote:

Thanks for the suggestion but can you tell me what is actually going wrong.

I dont understand only data transfer takes place in only one direction


Regarding to your configuration, there is no triggering mechanism to read data. In order to design such mechanisms you need to know how the modules interact with each other.

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Explorer
Explorer
7,640 Views
Registered: ‎12-05-2012

Re: Basic question: Axi single port BRAM READ OPERATION

I have an interrupt from an output port which starts the data transfer from bram to ddr3. Immediatly after this transfer I print the data in the ddr3 it looks fine next I send data back from there thats it.

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Scholar markcurry
Scholar
7,619 Views
Registered: ‎09-16-2009

Re: Basic question: Axi single port BRAM READ OPERATION

Pruthvi,

 

This thread is all over the place.  After reading two pages I'm unsure of the most basic parts of your question. We're not mind-readers!  Step back and give us details on what you're doing.  Some of the responses indicate you're debugging things completely unrelated to the subject or your first post.

 

Basic things like - foremost in my mind - are you debugging using real hardware or are you simulating?  I've read both pages of this thread twice, and to tell the truth, I'm unsure where you're debugging.  Some of your response seem to indicated a level of observabillity only available with simulation.  But other responses seeem to indicated you're running on HW. 

 

You indicate in some places that you "cannot read any data".  What does this mean?  Are your reads corrupted - or do the reads out-right fail somehow (i.e. hang?)  Are just some bits miscomparing, or the whole read data miscompare?  Is the miscompared read data consistent (i.e. your always read the same value)?

 

Sounds like you're doing some DMA operations.  Detail this better.   How do you know the writes are working?  (You must be reading somehow to convince yourself that the "writes are fine".

 

I can guess at a lot of what you're doing.  But it's just guesses, and I've got to make too many.  Help us help you.

 

--Mark

 

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Explorer
Explorer
7,615 Views
Registered: ‎12-05-2012

Re: Basic question: Axi single port BRAM READ OPERATION

Hello Mark,

 

Sorry for confusing.

 

I actually am running my application on the HW.  I can say that writing to BRAM works fine, as I have really send data from external devices and could recieve the data properly in DDR3 ram(via BRAM).

 

When I want to do exactly now is to read the data from ddr3 ram through BRAM but I recieve only zeroes in my external devices. My external device is running fine as I have send dummy data from PL .

 

As everything in the PL is running fine I am sure now that I am not recieving any data from BRAM.

 

Hence, I wanted to know what signals need to be asserted on BRAM PL interface side to read data from DDR3.(This is my first doubt)

 

2nd Question : I haven't flushed the address range of source address in my application where cdma transfers take place between source address(ddr3 ram address) and destination address(BRAM CONTROLLER). So I want to know what flush range actually does?? I cant invalidate the range of destination address as it is not in the PS.

 

So I am really confused with this as I have tried everything I could with my little experience 

 

Kindly forgive me

 

Regards

Pruthvi

 

 

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Scholar markcurry
Scholar
7,611 Views
Registered: ‎09-16-2009

Re: Basic question: Axi single port BRAM READ OPERATION


@pruthvi_8889 wrote:

Hello Mark,

 

Sorry for confusing.

 

I actually am running my application on the HW.  I can say that writing to BRAM works fine, as I have really send data from external devices and could recieve the data properly in DDR3 ram(via BRAM).

 

 


 

The DDR has only one port.  So you say here that you ARE reading the DDR3 just fine, and its contents are good.  Your trouble has nothing to do with DDR3 reads.  Or at least not obviously.

 

My guess is those reads are just single processor reads, and the read which you think is failing is the DMA read of the DDR?

 

Another suggestion - avoid uncommon acronymns.  I'm pretty sure when you say "PL", and "PS" you're differentiating between the hard core ARM on the Zynq, and the programmable logic in the rest of the FPGA.  If this question were on the Zynq forum it'd probably be appropriate, but I don't remember which is which, and Xilinx' names for each, and am too lazy to go google it.  "PS" = Processor Subsystem, "PL" = Programmable Logic? 

 

Here's what I think you're doing:  (And here's how you should've started this post):

 

1.  You are DMAing some data to DDR (from where - a BRAM?)

2.  You read the data from DDR (without the DMA) and the contents look good.  (Is this just  a READ command from the Arm, or something else?).  So DDR read operation is fine (at least a single read at a time).

3.  You DMA the data from DDR to a BRAM (same BRAM as above?)

4.  You read  the data from the BRAM and it's not what you expect?  (Same question on the READ command - just a read from the ARM?)

5.  You've verified that you can write data to the BRAM via some other method, and read it back correcty?

 

Is this summary correct?

 

Last question - maybe should be the first - HAVE YOU SIMULATED this operation?  You should.

 

You're suspecting cache interference - which is an entirely valid concern.  But we can't help confirm or dismiss this suspicion on the information you've provided.

 

--Mark

 

 

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Explorer
Explorer
7,596 Views
Registered: ‎12-05-2012

Re: Basic question: Axi single port BRAM READ OPERATION

1.  You are DMAing some data to DDR (from where - a BRAM?)

2.  You read the data from DDR (without the DMA) and the contents look good.  (Is this just  a READ command from the Arm, or something else?).  So DDR read operation is fine (at least a single read at a time).

3.  You DMA the data from DDR to a BRAM (same BRAM as above?)

4.  You read  the data from the BRAM and it's not what you expect?  (Same question on the READ command - just a read from the ARM?)

5.  You've verified that you can write data to the BRAM via some other method, and read it back correcty?

 

 

I will explain point by point

1st question answer: Yes I dma data to ddr from BRAM (NOTE: BRAM IS IN fpga, look in to my previous posts about my embedded set up).

 

2nd Question: I print the data in SDK console(in the ARM) and it is the same.

 

3rd Answer : Yes!!! DMA the data using the same BRAM.

 

4th Answer: I read the data in my external device attached to it. I only recieved zeroes.(NOTE: I tried sending dummy data from FPGA to external device it works fine).

 

5th answer: As I already told you I just dma the data to DDR and print the data in that address. That is how I verify.

 

 

Apart from that I tried to invalidate the range of address in DDR and flushed the cache but nothing new happened. I always recieve zeroes.

 

NOTE:The application for transferring data is written in Xilinx standalone environment using the basic examples of cdma provided by Xilinx

 

I will place a scope on monday and see what happens that is my next step.

 

The BRAM IS NOT IN THE PROCESSOR SYSTEM it is hanging in the Programming logic and made available for VHDL modules to write and read data.addreses.jpgbus_interfaces.jpgExternalports.jpg

 

 

Regards

Pruthvi

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Scholar markcurry
Scholar
6,361 Views
Registered: ‎09-16-2009

Re: Basic question: Axi single port BRAM READ OPERATION


@pruthvi_8889 wrote:

1.  You are DMAing some data to DDR (from where - a BRAM?)

2.  You read the data from DDR (without the DMA) and the contents look good.  (Is this just  a READ command from the Arm, or something else?).  So DDR read operation is fine (at least a single read at a time).

3.  You DMA the data from DDR to a BRAM (same BRAM as above?)

4.  You read  the data from the BRAM and it's not what you expect?  (Same question on the READ command - just a read from the ARM?)

5.  You've verified that you can write data to the BRAM via some other method, and read it back correcty?

 

 

I will explain point by point

1st question answer: Yes I dma data to ddr from BRAM (NOTE: BRAM IS IN fpga, look in to my previous posts about my embedded set up).

 

2nd Question: I print the data in SDK console(in the ARM) and it is the same.

 


 

This means the READS from DDR are fine.  In fact, this also confirms that you're correctly invalidating  the cache to the DDR as the DMA write happened without cache knowledge.  That you're able to read the correct values here means you've correctly invalidated the processor read cache to the DDR.

 

 


@ pruthvi_8889 wrote:

 

 3rd Answer : Yes!!! DMA the data using the same BRAM.

 

4th Answer: I read the data in my external device attached to it. I only recieved zeroes.(NOTE: I tried sending dummy data from FPGA to external device it works fine).

 

5th answer: As I already told you I just dma the data to DDR and print the data in that address. That is how I verify.

 

Apart from that I tried to invalidate the range of address in DDR and flushed the cache but nothing new happened. I always recieve zeroes.

 


 

You're reading from BRAM at this point NOT DDR.  Is the BRAM cached too? I don't know.  If it is, you need to invalidate its memory range too (it's contents will have changed without the cache controllers knowledge). 

 

Does the content of the BRAM change when you do the DMA back to BRAM?  i.e. preinitialize the BRAM to some other value.  Does it change to all zeros after the DMA?  i.e. is the DMA changing those BRAM locations at all? 

 

You can debug this with Chipscope.  A sim may be easier.

 

Good luck.

 

--Mark

 

 

Explorer
Explorer
6,353 Views
Registered: ‎12-05-2012

Re: Basic question: Axi single port BRAM READ OPERATION

Hello Mark,

 

I have a small doubt. I was reading through this manual "http://www.xilinx.com/support/documentation/user_guides/ug473_7Series_Memory_Resources.pdf"

"When WE is inactive and EN is active, a read operation 
occurs, and the contents of the memory cells referenced by the address bus appear on the 
data-out bus."
 
So I wanted to know what is the referenced address?? (Is it the address of BRAM Controller and increment by 4 for burst read operation??) 
 
I was interested by this because while writing data in BRAM. I sent address starting with zeroes and later incrementing by 4.
 
Any idea about this address scheme??
 
Regards
Pruthvi 
 
 
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Xilinx Employee
Xilinx Employee
6,348 Views
Registered: ‎01-03-2008

Re: Basic question: Axi single port BRAM READ OPERATION

The documentation is referring to the value that is on the address pins of the BlockRAM.
------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
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Explorer
Explorer
6,346 Views
Registered: ‎12-05-2012

Re: Basic question: Axi single port BRAM READ OPERATION

Hello Mcgett,

 

Thanks for your reply.

But, still not clear I actually should manually send the address from FPGA . I dont understand what address in this case.

 

Does this address correspond to the address of AXI BRAM controller??

 

Regards

Pruthvi

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Explorer
Explorer
6,325 Views
Registered: ‎12-05-2012

Re: Basic question: Axi single port BRAM READ OPERATION

Hello Everyone,

 

This is my chipscope waveform. I see data flow but no data recieved through BRAM.(In my application I first write data from BRAM to DDR3 and then the viceversa(DDR3 to BRAM)).

 

Any suggestion would be helpful

 

chipscope.png

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Explorer
Explorer
6,309 Views
Registered: ‎12-05-2012

Re: Basic question: Axi single port BRAM READ OPERATION

Hello Everyone,

 

After chipscope I understand that the mistake lies with BRAM.

 

Can some one tell if the contraol signals generated in VHDL are correct.

 

architecture Behavioral of feed_BRAM is
signal temp_Enable :std_logic := '1';

 signal temp_WEN : std_logic_vector(3 downto 0) := "1111";
 signal temp_LED : std_logic_vector(3 downto 0) := "1111";


signal address_12bit_int    : std_logic_vector (31 downto 0):=(others=>'0');
signal address_12bit_read   : std_logic_vector (31 downto 0):="00000000000000000000000000000000";
signal IN_data       : std_logic_vector (31 downto 0):="00000000000000000000000000000000";
signal temp_address_gen       : std_logic_vector (31 downto 0):=(others=>'0');

begin
 adress_gen: process(clk_1) //(WRITE DATA TO BRAM)
   begin
  
   if rising_edge(clk_1) then
    Enable <= '1';
    if ((flag_A = '1')and (address = '1'))  then
       address_12bit_read <= (others=>'0');
     address_12bit_int   <= address_12bit_int + 4;
   
       IN_data <= data_fx3;
       temp_WEN            <= "1111";
       end if;
      
     if ((flag_A = '0') and (address = '0'))   then // (READ DATA FROM BRAM)
             address_12bit_int   <= (others=>'0');
             address_12bit_read <=  address_12bit_read + 1;
                          
             temp_WEN            <= "0000";
             temp_LED            <= "0000";
             IN_data <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
              
      
       
    end if;
  end if;
end process;
 
  process(clk_1)
   begin
    if rising_edge(clk_1) then
      if (address = '1') then
              temp_address_gen <=  address_12bit_int ;
    elsif (address = '0') then
              temp_address_gen <=  address_12bit_read ; 
          end if;
      end if;
   end process;  

address_gen <= temp_address_gen ;
WEN <= temp_WEN;
data_BRAM <=  IN_data;

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Explorer
Explorer
6,279 Views
Registered: ‎12-05-2012

Re: Basic question: Axi single port BRAM READ OPERATION

Hello Xilinx Team,

 

I have tried what all I could and fed up now...:(

 

WHat I have tried....

 

As told earlier.. I make port B/A external and write data in to BRAM from VHDL MODULES and transfer to ddr(ddr is in Zynq PS) using cdma. This is successful

 

But the opposite read operation fails.

 

Then what I did was connected an other axi bram controller(single port) to M_AXI_GP0 and connected to the same bram block to port B. When I transmit data I can recieve the data in this BRAM also.(I have printed in my sdk application all values in this bram controller address and its running perfectly)

 

But I still cant understand why I cant read data from BRAM block when writing to BRAM is successful.

 

I WANT TO ASK ONLY ONE THING DID XILINX EMPLOYEES TRY DOING THIS???

 

What are the other ways to write data in to PL from Zynq PS.

 

 

PS: I am using Xilinx 14.3 and axi bram controller version 1.03a

 

 

Regards,

Pruthvi

 

 

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Observer zasxcd
Observer
2,522 Views
Registered: ‎05-28-2017

Re: Basic question: Axi single port BRAM READ OPERATION

@pruthvi_8889 Hi. Did you find a solution to this? I'm facing the same problem. I'm able to write to BRAM properly but not able to read from it.It's giving all zeroes. Same as your case. Can you please suggest what you did to solve this?

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Observer novec_16
Observer
2,479 Views
Registered: ‎04-25-2017

Re: Basic question: Axi single port BRAM READ OPERATION

Hi pruthvi_8889,

I might be wrong since didn't read the whole thread but It seems that the BRAM is connected to DDR via CDMA. In this configuration PL is an AXI master and can read and write to DDR bypassing the processor.

It is not clear how the processor can read/write to BRAM. There are no components connecting PS to BRAM. The only BRAM port is under control of PL VHDL module.

If this picture is correct I would add the second port to BRAM and a BRAM controller. These two components provide easy independent channel from the processor to BRAM. Processor doesn't need anything to read/write DDR but simple C code the same code but to a BRAM address can be used to write to the BRAM.

It is not clear what were reasons for not doing it from the start.

Good luck!

 

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Observer zasxcd
Observer
2,410 Views
Registered: ‎05-28-2017

Re: Basic question: Axi single port BRAM READ OPERATION

@novec_16 Hi, I am writing my data from Processing system to BRAM via AXI BRAM Controller and Programmable logic core that I have genereted via HLS version 2014.2 is reading from it. But the read is destructive as it is reading all zeroes. I checked that my core is able to write to BRAM properly. Can you please help me here? I am facing the same problem and don't know how to proceed. 

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