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Observer novec_16
Observer
1,466 Views
Registered: ‎04-25-2017

Re: Basic question: Axi single port BRAM READ OPERATION

@zasxcd,

It is hardly possible be helpful if I need to guess your architecture and code. There are too many things can be screwed up.

The first question: does Vivado find errors in your design? I assume not.

Do you have successful read/write to BRAM from PL?

Can you read/write BRAM from PS without PL module? If not then make it to work. You need to create a separate test block diagram which includes only PS, BRAM controller, BRAM memory generator and, of course, AXI memory interconnect. This should work flawlessly.

After these two tests are working you can combine them in one design. However, make sure that BRAM is DUAL Port. Port A you can connect to the BRAM controller and Port B to PL module. You can create HDL module with all signals needed for communication with BRAM. Then you just wire HDL module with BRAM as any other IP module. In this case Vivado will do BRAM instantiation for the HDL module.

Please understand that people don't have time to do guess work. If you want specific answer you need to describe conditions and goals.

Hope this helps, good luck!

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Observer zasxcd
Observer
1,442 Views
Registered: ‎05-28-2017

Re: Basic question: Axi single port BRAM READ OPERATION

@novec_16 Hi. Sorry for not being specific. I had created a separate thread here (https://forums.xilinx.com/t5/High-Level-Synthesis-HLS/BRAM-Interface-in-HLS/td-p/776201) since I wasn't able to find any solution, but I couldn't get any reply.

 

I will start with explaining what I'm trying to do here too. So, I have written this code in HLS for a core that takes 1-D data as input from BRAM1 (dual port with PORT-A connected to custom IP core and PORT-B to the PS) stores it in 1-D output Y into BRAM2(also dual port with PORT-A connected to custom IP core and PORT-B to the PS). 

 

My HLS code: 

void core(float X[100],float Y[100])
{
#pragma HLS INTERFACE s_axilite port=return bundle=CRTL_BUS
#pragma HLS INTERFACE bram port=x
#pragma HLS INTERFACE bram port=res

for(int i=0;i<100;i++)
Y[i]=X[i];

 }

 

Now, instead of this if I force a constant to Y: 

void core(float X[100],float Y[100])
{
#pragma HLS INTERFACE s_axilite port=return bundle=CRTL_BUS
#pragma HLS INTERFACE bram port=x
#pragma HLS INTERFACE bram port=res

for(int i=0;i<100;i++)
Y[i]=2.0f;

 }

I'm able to see that PL is able to write to the BRAM properly. 

 

SDK code: 

#include<stdio.h>
#include<xcore.h>
#include"xparameters.h"

float *XHW= (float *)0x40000000;
float *resHW=(float *)0x40010000;

XCore doCore;
XCore_Config *doCore_Cfg;

void init_Core()
{
int status=0;
print("Initializing Core......\n");
doCore_Cfg= XCore_LookupConfig(XPAR_CORE_0_DEVICE_ID);
if(doCore_Cfg)
{
status=XCore_CfgInitialize(&doCore,doCore_Cfg);
if(status!=XST_SUCCESS)
{
print("Failed to initialize\n");
}
}
}

//software version

void Core(float X[100],float res[100])
{
res[i]=X[i];
}

int main()
{
init_Core();
print("Test Bram...");

float XSW[100];
float resSW[100];
int i;

for(i=0;i<100;i++)
{
XSW[i]=i;
XHW[1]=i;  
resHW[i]=i; //trying to write to BRAM2 to check if PS is able to write into it properly
}
int k;
print("Input Before...");
for(k=0;k<100;k++)
{
printf("SW=%f\t,HW=%f\t,resHW=%f\n",XSW[i],XHW[i],resHW[i]);
}

Core(XSW,resSW); //software
XCore_Start(&doCore); 
while(!XCore_IsDone(&doCore)); //hardware

print("Output");
for(k=0;k<100;k++)
{
printf("SW=%f\t,HW=%f\n",resSW[i],resHW[i]);
}
return 0;
}

I have attached image before the core starts. I can see Software input(SW), Hardware input (HW), and resHW(in BRAM2 before execution of core) as expected. This means PS is able to write/read to/from both BRAMs properly.

After the core gets executed, as seen in the image AFTER: The software ouput is as expected, but HW output(resHW stored in BRAM2) goes to all zeroes. Which indicates PL has not read from BRAM1 properly.

 

I'm also attaching the schematic for proper understanding of what I'm doing.  

 

Answer to your first question: No, I did not get any errors in the design. 

Answer for the second question: Write from PL to BRAM is fine. But read is not proper. 

Third answer: Yes, read/write between PS and BRAM is just fine. 

 

Vivado HLS version is 2014.2

Vivado version is 2014.2 

 

Please please help me here, I haven't been able to figure out the problem. 

Sorry for posting it here, despite of the thread created, but I am not getting any reply from anywhere.

Before.PNG
After.PNG
Capture.PNG
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Observer novec_16
Observer
1,420 Views
Registered: ‎04-25-2017

Re: Basic question: Axi single port BRAM READ OPERATION

Hi @zasxcd,

 

1. It think your SDK code is not aware of BRAM. For using BRAM and DDR typically people add something like this:

 

#define BRAM_MEMORY XPAR_AXI_BRAM_CTRL_0_S_AXI_BASEADDR
#define DDR_MEMORY XPAR_PS7_DDR_0_S_AXI_BASEADDR+0x00030000

 

u32 * source, * destination;

u32 * destination  = (u32 *) DDR_MEMORY;
u32 * source = (u32 *) BRAM_MEMORY;

 

copying BRAM to DDR:

        for(i = 0 ; i < BRAM_SIZE ; i++)
            *(destination + i) = *(source + i);

 

2. Check how your core IP was implemented, particularly, interface signals. Simple check is by clicking on the "+" sign at the end of x_PORT A designator. All signals should be available and be connected to the corresponding signals on the BRAM block.

Good luck!

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Highlighted
Observer zasxcd
Observer
1,387 Views
Registered: ‎05-28-2017

Re: Basic question: Axi single port BRAM READ OPERATION

@novec_16 Hi thanks for your reply. My BRAM to DDR transfer of data and viceversa is working fine.  My problem is PL core is not reading the data from BRAM. So my destination is PL and source is BRAM...should I specify the address for PL core instead of DDR?

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Observer novec_16
Observer
1,376 Views
Registered: ‎04-25-2017

Re: Basic question: Axi single port BRAM READ OPERATION

1. How do you verify reading and writing to BRAM?

2. What does it mean "not reading" zero values or random numbers?

3. Inspect your HDL code and check it against Xilinx templates. It worked for me.

 

If your HDL code follows Xilinx templates you can rule out coding mistake and in this case most likely is an error in addressing.

My approach is to make a small test project and fix all youe core - BRAM issues.

 

That's about all I can suggest.

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