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Newbie aalmont0
Newbie
609 Views
Registered: ‎03-07-2018

Basys 3 Seven Segment Display issue

Hey all,

I'm new to VHDL and attempting to program my board to display hex on the seven segment display using switches. I've managed to get the numbers to appear on the display, but have ran into two problems. I'd like the numbers to appear only on one display, not all of them. I thought setting "an <= "1110";" in the top file would give the desired result but I must be missing something. The second problem I'm having is activating btnC should display a negative sign, but doesn't. I tried port mapping negative to btnC and that didn't work. I've been troubleshooting for hours, any assistance would be greatly appreciated. Thanks!

 

sevenSegDecoder

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity sevenSegDecoder is
    Port ( sw       : in STD_LOGIC_VECTOR (3 downto 0);
           seg      : out STD_LOGIC_VECTOR (0 to 6);
           negative : in STD_LOGIC);
end sevenSegDecoder;

architecture Behavioral of sevenSegDecoder is

begin

    process(sw)
        begin
        if negative='1' then
            case sw is
                   when "0000" => seg <= "0000001"; --0
                   when "0001" => seg <= "1001111";
                   when "0010" => seg <= "0010010";
                   when "0011" => seg <= "0000110";
                   when "0100" => seg <= "1001100";
                   when "0101" => seg <= "0100100";
                   when "0110" => seg <= "0100000";
                   when "0111" => seg <= "0001111";
                   when "1000" => seg <= "0000000";
                   when "1001" => seg <= "0001100";
                   when "1010" => seg <= "0001000";
                   when "1011" => seg <= "1100000";
                   when "1100" => seg <= "0110001";
                   when "1101" => seg <= "1000010";
                   when "1110" => seg <= "0110000";
                   when "1111" => seg <= "0111000"; --F
    
    end case;
    
    end if;    

end process;

end Behavioral; 

Top file

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity topSevenSeg is
    Port ( sw : in STD_LOGIC_VECTOR (3 downto 0);
           btnC : in STD_LOGIC;
           seg : out STD_LOGIC_VECTOR (0 to 6);
           an : out STD_LOGIC_VECTOR (3 downto 0)
         );
end topSevenSeg;

architecture Behavioral of topSevenSeg is

    component sevenSegDecoder
    port (
           sw       : in STD_LOGIC_VECTOR (3 downto 0);
           seg      : out STD_LOGIC_VECTOR (0 to 6);
           negative : in STD_LOGIC
         );
    end component;
   

begin

    an <= "1110";

ins: sevenSegDecoder port map (
            sw => sw,
            seg => seg,
            negative => btnC
);

end Behavioral;

Constraints

#switches
set_property PACKAGE_PIN V17 [get_ports {sw[0]}]					
set_property PACKAGE_PIN V16 [get_ports {sw[1]}]					
set_property PACKAGE_PIN W16 [get_ports {sw[2]}]					
set_property PACKAGE_PIN W17 [get_ports {sw[3]}]
#segment display
set_property PACKAGE_PIN W7 [get_ports {seg[0]}]					
set_property PACKAGE_PIN W6 [get_ports {seg[1]}]					
set_property PACKAGE_PIN U8 [get_ports {seg[2]}]					
set_property PACKAGE_PIN V8 [get_ports {seg[3]}]					
set_property PACKAGE_PIN U5 [get_ports {seg[4]}]					
set_property PACKAGE_PIN V5 [get_ports {seg[5]}]					
set_property PACKAGE_PIN U7 [get_ports {seg[6]}]

set_property PACKAGE_PIN U2 [get_ports {an[0]}]					
set_property PACKAGE_PIN U4 [get_ports {an[1]}]					
set_property PACKAGE_PIN V4 [get_ports {an[2]}]					
set_property PACKAGE_PIN W4 [get_ports {an[3]}]					
#buttons
set_property PACKAGE_PIN U18 [get_ports btnC]		
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1 Reply
Moderator
Moderator
543 Views
Registered: ‎07-21-2014

Re: Basys 3 Seven Segment Display issue

@aalmont0

 

Did you verify the functionality with a testbench? If not, please create a testbench and test the functionality of the RTL code.

 

Thanks,

Anusheel

Thanks
Anusheel
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