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tip.can19
Observer
Observer
1,710 Views
Registered: ‎10-23-2018

Beginner Question: Why not 3 input AND gate?

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Hi,

Why my code is not inferring 3-input and gate?

`timescale 1ns / 1ps
module gates(input a,b,e,output [0:3] d);
and p1(d[0],a,b,e);//, p2(d[1],a,b,e), p3(d[2],a,b,e), p4(d[3],a,b,e);
endmodule

2IP.PNG

Thank you,

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Accepted Solutions
avrumw
Guide
Guide
1,523 Views
Registered: ‎01-23-2009

As @eilert said, the elaborated design is purely an intermediate step; it is a representation of your design using generic technology gates prior to optimization and mapping to Xilinx Basic ELements (BELs). Since it is not a final representation of the design, the cells it uses to represent it is whatever is convenient - you will find things that are both simpler than the eventual mapping (as you have seen with the 2 input ANDs) and significantly more complex than the final mapping (things like arbitrarily wide multiplexers, multipliers, adders and incrementers, comparitors, etc...).

I am pretty sure that there is no definitive list of what the elaborated netlist can be made of - again, it is purely an intermediate step which is, generally, of little use to the designer other than to "see" what the tool understood of your RTL.

Why do you care?

Regardless of whether the elaborated design showed it as two 2-input AND gates, or one 3-input AND gate will not affect how the tool will eventually map it to a LUT. A LUT can be used to map any arbitrarily complex combinatorial function of up to 6 inputs (and some combinations of up to two functions of 5 or less inputs) - almost all gates in the elaborated design will end up getting grouped into larger combinatorial functions and mapped to LUTs.

Avrum

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6 Replies
rshekhaw
Xilinx Employee
Xilinx Employee
1,634 Views
Registered: ‎05-22-2018

Hi @tip.can19 ,

As per my understanding, i don't think Xilinx primitive sub groups or type have 3 input RTL_GATE.

Thanks,

Raj

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tip.can19
Observer
Observer
1,597 Views
Registered: ‎10-23-2018

Hi Raj,

So there is no 3-input AND primitive in Xilinx resources? Can you please help me confirm this via any datasheet? Is it same for higher end devices?

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eilert
Teacher
Teacher
1,576 Views
Registered: ‎08-14-2007

Hi,

you just looked at the RTL analysis schematic.

This will just show you how the VHDL tool interprests your HDL code.

Do a synthesis run and look at the sysnthesis shematic, there you will see how your design will appear in the FPGA.

And there will only be LUTs, FFs and some special blocks like Carry4, DSP and BlockRAM etc.

So, whatever combinatorical code you write in some HDL, if has 6 inputs or less, it will be placed in a single LUT anyway. (For Series 6 and 7 FPGAs, that is)

 

For Series 7 Devices you find available Macros in these User Guides: UG768 and UG799

However, instantiating any N-input logic cate will not give you any advantage over using logic operators. In the end it's all a bunch of LUTs, highly optimized by the synthesis software.

 

Have a nice synthesis

  Eilert

tip.can19
Observer
Observer
1,531 Views
Registered: ‎10-23-2018

Hi @eilert,

Thank you for your reply. Actually, I am aware that tool synthesizes to FPGA resources and LUTs in case of combinational logic. My issue was understanding what are the resources in elaborated design. Like as we can see, the rtl represents 3-input and gate, but tool shows using 2-input gates. I know this will be mapped to LUT. I was wondering where would I find datasheet or user guide to know what limits are for elaborated design or is there a three input gate available for mapping? Xilinx pointed out above that there might not be any 3-input primitive for use. I was hoping to have the same guide/datasheet.

Regards,

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avrumw
Guide
Guide
1,524 Views
Registered: ‎01-23-2009

As @eilert said, the elaborated design is purely an intermediate step; it is a representation of your design using generic technology gates prior to optimization and mapping to Xilinx Basic ELements (BELs). Since it is not a final representation of the design, the cells it uses to represent it is whatever is convenient - you will find things that are both simpler than the eventual mapping (as you have seen with the 2 input ANDs) and significantly more complex than the final mapping (things like arbitrarily wide multiplexers, multipliers, adders and incrementers, comparitors, etc...).

I am pretty sure that there is no definitive list of what the elaborated netlist can be made of - again, it is purely an intermediate step which is, generally, of little use to the designer other than to "see" what the tool understood of your RTL.

Why do you care?

Regardless of whether the elaborated design showed it as two 2-input AND gates, or one 3-input AND gate will not affect how the tool will eventually map it to a LUT. A LUT can be used to map any arbitrarily complex combinatorial function of up to 6 inputs (and some combinations of up to two functions of 5 or less inputs) - almost all gates in the elaborated design will end up getting grouped into larger combinatorial functions and mapped to LUTs.

Avrum

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tip.can19
Observer
Observer
1,477 Views
Registered: ‎10-23-2018

Thanks @avrumw! Now I understand this much better.

Thanks @eilert (and others) for your much needed help and inputs too.

Regards,

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