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dck140130
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Registered: ‎02-06-2018

Behavioral (all p) vs Structural (switches, buttons, leds....), mapping floorplan to desired switches?

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Context:

I AM UBER NEOPHYTE, using spartan3e 100, programming in xilinks with verilog

 

Goal:

use behavioral verilog to

increment 3bit input when selector is low and

decrement 3bit input when selector is high

output 4 bit solution

 

Please reference attachments

Problem:

while in simulation mode

{

no errors when Behavioral Checked Syntax

no errors during Simulate Behavioral Model, although iSim does not show last testbench scenario of id: 1 a: 111 found in attached tb...WHY!?! :- ( 

}

 

then in Implementation mode

{

I get the following error when trying to create floor plan

 

WARNING:Xst:905 - "BVIncDec.v" line 28: One or more signals are missing in the sensitivity list of always block. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<a>
ERROR:Xst:855 - "BVIncDec.v" line 31: Unsupported procedural assignment for signal <f>.

}

 

Questions:

Why iSim not running the last scenario in my testbench when I "elaborate" it and adjust the timing diagram to 2us?

What about my code is dysfunctional?

What is a sensitivity list?

Why when I code behaviorally rather than structurally do i have issues mapping the floorplan to the desired switches?

 

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dck140130
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Registered: ‎02-06-2018

FINAL UPDATE

 

Questions:

Why iSim not running the last scenario in my testbench when I "elaborate" it and adjust the timing diagram to 2us?

-reason was that the always block was being triggered by wrong parameter

What about my code is dysfunctional?

-always block parameter was id, id does not change except once, thus output only changed once

-id was not passed to the outputs and so when mapped to board it was not possible to control if id was high or low

What is a sensitivity list?

-it is the parameters contained within the always block i.e. always @ (sensitivity list)

Why when I code behaviorally rather than structurally do i have issues mapping the floorplan to the desired switches?

-design properties did not have the cp130 board selected, it was some other model.. I think VL something.

 

I'd like to say that the professors that commented in this stream have acted as gatekeepers to knowledge. They in no way motivated or directed the learner and instead expressed a classist/elitist condescension with remarks like "couldn't leave the student in ignorance" and "i'm feeling generous". They must have stereotyped me as an 18 year old kid, unbeknownst that I am a 31 year old COMBAT vet with 3 undergad degrees from highly regarded liberal arts institutions that has worked in industry for some time and could comfortably retire tomorrow. If it was up to me, I would have the time to read a verilog manual front to back. I pay to be fed knowledge, not to teach myself. I am happy to teach myself, but would need to not be taking 18 hours, working, exercising, and navigating blockheads. 

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austin
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Registered: ‎02-27-2008

We generally do not do homework for you here in the forums,

 

Unless someone really has some time on their hands and feels generous.  As with many professors, if teaching this quarter or semester (as I am), we do scan the forums which apply to our courses (I tell my students to read this forum, and ask questions).  I certainly would not look kindly if my student got their homework done for them by a forum.  Learning what they did wrong is fair, though (someone replies with just the error in your code -- you still have to fix it, and get it to work).

 

So, here's hoping someone points out the error in you code, pointing to to a resource to understand what is wrong, so you learn how to fix it.

Austin Lesea
Principal Engineer
Xilinx San Jose
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dck140130
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I appreciate your advice. I think it is clear that I have a desire to learn and am giving an honest effort to try before seeking assistance in the face of almost no instruction from the institution I am paying to teach me, and in the face of the alternative of plagiarism. If we share affialtions we should speak in person.
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austin
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Just a friendly comment,

 

That is all.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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mike_james_lewis
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Registered: ‎09-01-2015

I'm feeling generous ...

 

remove "assign" in the two places you've used it.

 

Mike

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austin
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Registered: ‎02-27-2008

Ahhh,

 

Another fellow teacher.  Just couldn't leave the student in verilog ignorance (or any of use who are following along).

 

I must say I discover all kinds of stuff I would never imagine using (and getting me into trouble).  I remind my students that verilog (VHDL) is creating HARDWARE (gates, wires, flip-flops for a synchronous logic circuit) so think HARDWARE, not SOFTWARE.  Not sure that helps, but it makes me feel better.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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dck140130
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Registered: ‎02-06-2018

Thank you for your contribution.

 

My apologies, I meant to include in my initial statement that I originally had the code without using the keyword assign.

While the syntax check returns without error, the simulation shows no change to the output.

When I added the keyword assign, then the output varied.

 

I'm just sitting down with this again. I will share what I learn.

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dck140130
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UPDATE:
-tried creating parameter to replace 1 in the function with
-tried posedge or negedge prior to id in the always parameters
-realized that always acts as the mechanism for executing the block and that id is not a clock and therefore always block has no reason to execute until my testbench changes id from 0 to 1... Which is why output is 0001 for all 3 bit combinations until id goes high and so the always block executes and decrements the first three bit combination for while id is 1 which is 000, and so while id is 1 my output is static at 1111....

So new problem is wtf do I put in the always block so that my output executes for each set of testbench bit combinations?

I dont want to add a clock, although that'd work and be easy enough.

maybe could use two while loops, but still need always keyword to identify block or it isn't behavioral right? cant have always keyword without a parameter it would seem. Tried always @ (id), always @ (), and some other variations...

 

To answer my third question:

 

Appears the sensitivity list is the list of parameters you put in always.... always @ (sensitivity list is here)

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dck140130
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UPDATE2:
a is the input that changes and each time it changes it is desirable for the procedural instructions found inside the always block to be executed

set always parameter to a:
always @ (a)
with this change it does not appear to matter, at least in this instance for the sake of the timing diagram after running the simulation that using the keyword assign in front of the functions matters. maybe this affects switch assignment on the board?
problem solved!

remaining question:

Why when coding behaviorally rather than structurally do i have issues mapping the floorplan to the desired switches on the spartan board? It looks like most options arent even switches, maybe registers? idk yet, will update when I do.

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dck140130
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FINAL UPDATE

 

Questions:

Why iSim not running the last scenario in my testbench when I "elaborate" it and adjust the timing diagram to 2us?

-reason was that the always block was being triggered by wrong parameter

What about my code is dysfunctional?

-always block parameter was id, id does not change except once, thus output only changed once

-id was not passed to the outputs and so when mapped to board it was not possible to control if id was high or low

What is a sensitivity list?

-it is the parameters contained within the always block i.e. always @ (sensitivity list)

Why when I code behaviorally rather than structurally do i have issues mapping the floorplan to the desired switches?

-design properties did not have the cp130 board selected, it was some other model.. I think VL something.

 

I'd like to say that the professors that commented in this stream have acted as gatekeepers to knowledge. They in no way motivated or directed the learner and instead expressed a classist/elitist condescension with remarks like "couldn't leave the student in ignorance" and "i'm feeling generous". They must have stereotyped me as an 18 year old kid, unbeknownst that I am a 31 year old COMBAT vet with 3 undergad degrees from highly regarded liberal arts institutions that has worked in industry for some time and could comfortably retire tomorrow. If it was up to me, I would have the time to read a verilog manual front to back. I pay to be fed knowledge, not to teach myself. I am happy to teach myself, but would need to not be taking 18 hours, working, exercising, and navigating blockheads. 

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austin
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I apologize if I have offended you,

 

I am a professor (this quarter), so I am guilty of all that implies (I do know more than my students(.

 

I am also professional engineer employed since 1975. (I do acknowledge my customers are always right)

 

I presently do research, having last been an IC designer here at Xilinx.

 

I have the utmost respect for veterans.  One is part of my family.

 

I have provided support and guidance to  many DoD, Darpa, NSA, NRL programs in my career.  I have held clearances to participate in some of these programs in depth.

 

Xilinx devices are in virtually all military hardware, enabling our armed forces to fulfill their missions.

 

Again, I apologize for assuming you were a young student trying to get someone else to do your homework.  As a customer, you right (I am wrong),

 

This forum is intended to serve those engineers using Xilinx devices for commercial products.  We do not police who posts:  students and hobbyists also participate.  But questions are generally of the form: "x did not work, I have tried y, z, and w.  Examples. devices, logs below."

 

You may ask anything, but please understand what this forum is for and try not to be disappointed  if you do not get exactly what you wanted.

 

If you would like a list of books to read:  austin@xilinx.com

Austin Lesea
Principal Engineer
Xilinx San Jose
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