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Visitor thatsage
Visitor
339 Views
Registered: ‎11-25-2018

Behavioural Simulation and post-Synthesis Functional Simulation don't match

Hi, I'm tying to implement an algorithm in FPGA. I'm using Vivado, VHDL and target board for testing is BASYS3.

I'm having trouble finding the reason post-synthesis simulation (and the actual hardware as a result) doesn't match the behavioural simulation. The logic I've written is a single process operating every rising edge of a (divided) clock. The logic itself is asynchronous, but the output is synchronized through a register.

The RTL schematic is as I expect: asynchronous gates and adders and stuff like muxes and adders, ultimately leading to the final result which is fed to an output register.

The post-Synthesis schematic looks fine too, it creates LUTs and adders, ultimately leading to the final result which is fed to an output register.

Here is my main entity -

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity main is
    port (CLK100MHZ: in std_logic;
         in_string: in std_logic_vector(15 downto 0); -- switches 16 to 1
         current_c: out std_logic_vector(2 downto 0));
end main;

architecture Behavioral of main is

    constant size: integer:= 31; -- 127
    constant char_length: integer:= 8; 
    constant string_length: integer:= 4; -- 16 
    
    signal back_buffer: std_logic_vector (size downto 0);
    signal DIVCLK: std_logic:='0';
    signal count: integer range 0 to 100;
    
begin

back_buffer <= in_string (15 downto 12)& x"0" 
& in_string(11 downto 8) & x"0"
& in_string(7 downto 4) & x"0"
& in_string(3 downto 0) & x"0"; div_clk: process(CLK100MHZ) begin if rising_edge(CLK100MHZ) then count<=count+1; if count<49 then DIVCLK<='0'; elsif count<99 then DIVCLK<='1'; else count<=0; end if; end if; end process; LZC: process (DIVCLK) variable tp: integer range 0 to size; -- pointer to top variable bp: integer range 0 to size-char_length+1; -- point to bottom variable current_size: integer range 0 to char_length; variable max: integer range 0 to char_length; variable c: integer range 0 to string_length; -- reuslt variable total_size: integer range 0 to string_length; begin if rising_edge(DIVCLK) then total_size:=1; max:=0; c:=1; for i in 1 to string_length-1 loop if total_size<string_length then tp:=size; -- reset pointers bp:=size-char_length+1; max:=1; current_size:=1; c:=c+1; for scan in 1 to string_length-1 loop if (tp>size-char_length*total_size and total_size+max<string_length) then if back_buffer(size-char_length*total_size downto size-char_length*total_size-(tp-bp))=back_buffer(tp downto bp) then current_size:=((tp-bp)+1)/char_length+1; if current_size>max then max:=current_size; end if; bp:=bp-char_length; else -- move TP and BP down tp:=tp-char_length; bp:=tp-char_length+1; end if; end if; end loop; total_size:=total_size+max; end if; end loop; current_c<=std_logic_vector(to_unsigned(c,3)); end if; end process; end Behavioral;

Here are the results -

Screenshot from 2019-08-18 12-05-15.pngBehavioural Simulation

Screenshot from 2019-08-18 12-06-29.pngpost-Synthesis Functional Simulation

What could be the problem? Could it be a bug in Vivado?

EDIT: I added the project, if anyone takes a look I would really appreciate it..

 

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10 Replies
Scholar richardhead
Scholar
322 Views
Registered: ‎08-01-2012

Re: Behavioural Simulation and post-Synthesis Functional Simulation don't match

if rising_edge(DIVCLK) then

Theres your problem. Using a logic generated clock is bad design practice as it can lead to exactly the problems you are having.

Much better to use the original clock and create a divided clock enable instead.

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Scholar drjohnsmith
Scholar
314 Views
Registered: ‎07-09-2009

Re: Behavioural Simulation and post-Synthesis Functional Simulation don't match


dont use variables,

C programmers use variables , VHDL is hardware design language,

They have a place, but, not here
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Scholar dgisselq
Scholar
305 Views
Registered: ‎05-21-2015

Re: Behavioural Simulation and post-Synthesis Functional Simulation don't match

@thatsage,

That loop you are using, and the for loop within it, I do not think it does what you think it does.

Dan

Visitor thatsage
Visitor
290 Views
Registered: ‎11-25-2018

Re: Behavioural Simulation and post-Synthesis Functional Simulation don't match

Thanks for the help everyone.

richardhead-

I looked up clock enable division and did what I think you meant. The result is the same. Honestly, this doesn't really need a clock to begin with, since all the logic is combinational. If all I put in the sensitivity list is the input (back_buffer) instead, nothing changes either, so I don't think it's a timing issue (also, no warnings about timings).

drjohnsmith, dgisselq -

I'm a novice, but I do mostly understand processes, variables and what VHDL is - this is part of my B.Sc project (Electrical Engineering). What I'm trying to do is implement an algorithm through combinational logic. I'm using a process with variables so I can take advantage of for-loops and if-else statements for sake of scaleability, so that the tool would generate hardware that can resolve the algorithm for inputs of different (greater) lengths. Essentially, the logic required is a truth table - if the algorithm handles "4 inputs" (an input that's 4 bytes long) I could create the logic literally with 16 lines of code. Well, sort of. But I want code that is scalable, because it's not practical for me to write the say 256 lines 8 bytes would require or say even 16 bytes (not that I would necessarily need it that high).

Beyond that, it passes synthesis and there aren't any warnings or timing issues it would seem, writing bitstream is successful. If this should be wrong then it should already be wrong (and impossible) in behavioral simulation, or not pass synthesis. So that the two simulations don't match is still an issue in my opinion.

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Scholar drjohnsmith
Scholar
276 Views
Registered: ‎07-09-2009

Re: Behavioural Simulation and post-Synthesis Functional Simulation don't match

Most VHDL is adaptable, and does not use variables,

Simulation takes what you write,

For instance,

if you have sensitivity list errors, simulation marks them as warnings, and then ignores them,

You need to check out the warnings,
Also in simulation, you can not ( easily ) see the variables,

remember the difference between variables and signals. variables update immediately, whilst signals update on the next delta,

The are very different.

for instance , if you wanted to write a shift register,
I'd write

my_std_log_var <= my_std_log_var ( my_std_log_var -left -1 downto 0 ) & new_input;

Now that can be written using variables, and loops, but its normal not to, as the above is understood by all the tools and people,

Rember , ports into the entity, can be post enumerated,

so you can use
in_string: in std_logic_vector;

then in the code use
in_string'left to find out the length of the SLV.

you could then use things like
constant string_length integer <= in_string'left / 4;

or even use the log function from math real, as its a constant, its elaborated at compile time, so does not add extra to the code.


<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Scholar richardhead
Scholar
235 Views
Registered: ‎08-01-2012

Re: Behavioural Simulation and post-Synthesis Functional Simulation don't match

@thatsage 

This really seems to be a design problem, rather than synthesis or timing problem.

I assume you've written the code hoping to get a circuit. rather than designing a circuit and then writing the code. The first method is never going to work well - HDL has to be written with the circuit already designed. 

Visitor thatsage
Visitor
209 Views
Registered: ‎11-25-2018

Re: Behavioural Simulation and post-Synthesis Functional Simulation don't match


@richardhead wrote:

@thatsage 

This really seems to be a design problem, rather than synthesis or timing problem.

I assume you've written the code hoping to get a circuit. rather than designing a circuit and then writing the code. The first method is never going to work well - HDL has to be written with the circuit already designed. 


I guess that's the problem yeah. I know what I want is feasible since I can figure it out for shorter inputs, so I was hoping Vivado could figure out "generic variants" of different sizes for me. I guess I learned my lesson. The synthesis tool doesn't always understand what's going on - even when simulation seems to. Even when the RTL schematic makes it look like a sure thing.

I'm going to redsign this and put the outer for-loop on a clock. So instead of doing a for-loop inside of a for-loop, which is all intended to resolve in one clock, I'll have the inner loop still happening inside 1 clock but the outer loop would progress between clocks. I think that's the right direction.

The sad part is that, say for this example which is 4 bytes long, I can implement the truth-table and design the system explicitly. It's essentially a 6 inputs 1 output truth table with around half of the lines crossed out because some input combinations aren't posible, so the truth table would around 30 something rows. That approach should definitly be good to happen in 1 or 2 clocks. But the hard part is that I want something that can be scaled up to handle longer stuff, so filling in the truth table myself is impractical.

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Scholar richardhead
Scholar
202 Views
Registered: ‎08-01-2012

Re: Behavioural Simulation and post-Synthesis Functional Simulation don't match

I would say ditch the loop altogether initially.

Draw out the circuit you're trying to acheive on paper, or powerpoint or something. Dont just write the code and hope Vivado will create a circuit for you. It will convert pretty much whatever HDL you throw at it - however bad an inefficient it is - it will simply create the circuit that you wrote.

Scholar dgisselq
Scholar
184 Views
Registered: ‎05-21-2015

Re: Behavioural Simulation and post-Synthesis Functional Simulation don't match

As a matter of perspective, I often find FPGA design and data flow design go hand in hand.  Sure, you can design a core to operate on all of the elements of a string at once, but will all the elements of a string ever be present at the same time?

On the cores I've worked on, the memory bus is only ever 32-bits wide.  Yes, buses can be wider, but bear with me.  Because of this, I'd expect strings longer than 32-bits (4-bytes is a rather short string, especially when you include the terminating null character) to be passed piecemeal to a string processing core a couple bytes at a time.

Memory widths aren't limited to 32-bits, though, even if I've always limited them artificially.  Some memory and bus configurations will go up to 64, 128, or even 256 bits wide (or wider, but the routing and logic costs go up as the bus increases in width).  Even then, if you could process a string 256 bits at a time, you run into the hardware limit quickly that the bus isn't any bigger than that.  For any reasonably length string, longer than 32-bytes and probably much shorter than that, processing the entire string at once doesn't make any practical sense.

For all of these reasons, I would find that string processing has to be dealt with one (or more) characters at a time, but also in a pipelined fashion, rather than combinatorially.  Yes, this does create other problems, since you may now need to synchronize multiple stream processing pipelines together, but such a processing algorithm would be one I would find to be truly generic--not one that processes an entire string at once.

Dan

Visitor thatsage
Visitor
170 Views
Registered: ‎11-25-2018

Re: Behavioural Simulation and post-Synthesis Functional Simulation don't match

Thanks for the insight. As you've said, even if it did work and managed to process these "big" strings at once, bus is still a limiting factor, and why have the system wait until all data arrives if it can already start working after the first chunk arrives... Plus, being limited to relatively short strings may make all this work kind of useless application-wise anyway.

I'm restarting this part of the design, will make it work properly first in a serial manner and then working out ways to make parts of it parallel and improve performance.

Thanks everyone, I'm not choosing a specific answer because pretty much everyone helped me realize (and come to terms with the fact) that the issue is in the design itself which needs to be reworked. It's too convulted and complicated as it stands.

 

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