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steveclynes
Visitor
Visitor
4,039 Views
Registered: ‎11-17-2009

Bit field of a signal as a clock

Hi,

I have a std_logic_vector signal and an associated std_logic_vector signal which contains corresponding clock signals and I am trying to use 'generate' statements to create registered inputs for each input signal based on its own clock.

 

RegisterSPDIFIn : for i in 1 to 12 generatebegin  process  begin    wait until AudioClkIn(i)'event and AudioClkIn(i) = '1';    AudioInReg(i) <= AudioIn(i);  end process;

end generate RegisterSPDIFIn;

When I try to synthesize this code ISE fails, telling me that the process has multiple clocks in the wait statement.

Any thoughts what I am doing wrong?

Kind regards,

Steve

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3 Replies
bassman59
Historian
Historian
4,038 Views
Registered: ‎02-25-2008


steveclynes wrote:

Hi,

I have a std_logic_vector signal and an associated std_logic_vector signal which contains corresponding clock signals and I am trying to use 'generate' statements to create registered inputs for each input signal based on its own clock.

 

RegisterSPDIFIn : for i in 1 to 12 generate

begin
process  begin   
wait until AudioClkIn(i)'event and AudioClkIn(i) = '1';   
AudioInReg(i) <= AudioIn(i); 
end process;

end generate RegisterSPDIFIn;

 

When I try to synthesize this code ISE fails, telling me that the process has multiple clocks in the wait statement.

Any thoughts what I am doing wrong?

Kind regards,

Steve


 Don't use the wait-until construct. Use the standard synchronous process contstruct instead. The tools might just be confused.

 

Message Edited by bassman59 on 11-17-2009 10:11 AM
----------------------------Yes, I do this for a living.
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blaine
Xilinx Employee
Xilinx Employee
4,007 Views
Registered: ‎04-11-2008

Steve,

 

The synthesis tool can handle 'wait until' no problem.

 

You have multiple clocks inferred as a result of your generate statement however, the synthesis tool is probably incorrect here as i can see you have only one clock per process line. One thing to note is that you have missed the AudioClkIn off the sensitivity list, maybe this will fix this otherwise code what you are trying to do outside a generate statement. 

 

However, what you are doing might not be good FPGA design. Generally you do not want loads of clocks going around. I would look to synchronize to a single higher frequency clock. Maybe use the AudioClkIn as a data signal. Also Audio clocks are probably low frequency, maybe you can make use of time domain multiplexing and share resource.

 

JB

 

 

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steveclynes
Visitor
Visitor
4,000 Views
Registered: ‎11-17-2009

Thanks Guys.

 

I managed to work around this as suggested, by using a different construct.

 

RegisterSPDIFIn : for i in 1 to 12 generate

begin 

  process  (AudioClkIn, AudioIn)

  begin    

    if (AudioClkIn(i)'event and AudioClkIn(i) = '1') then

    begin

      AudioInReg(i) <= AudioIn(i); 

    end;

  end process;

end generate RegisterSPDIFIn;

(typed this from memory, so may not be 100% correct!!)

In my original code I did not need a sensitivity list since the process contained a wait.

Additionally, I cannot use a higher frequency clock since jitter is extremely important. I do actually transfer the data signal into a unified clock domain for processing then transfer it back to the source clock for final output.

Again, thanks both for your help. I really appreciate your time.

BR,

Steve

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