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Participant
Participant
12,064 Views
Registered: ‎11-21-2007

Bits Missing in Netlist after Synthesis

Using Vivado 2015.3. I created an extremely simple design which includes a 32-bit counter:

 

          reg [31:0] count;

After synthesis the 1st item under Nets in the Netlist is

 

         count_reg(25)

 

The 1st 7 bits are not enumerated. The synthesis log contains

 

      Detailed RTL Component Info :
      +---Registers :
                         16 Bit    Registers := 2     

 

so it recognizes my other 2 shorter registers. What happened to 'count'? I also tried shortening it to just fit the max count I'm allowing, but it still "ignores" the 1st 7 bits of that length. Further down in the Netlist the 1st 7 bits are enumerated as

 

       count_reg_n_0[0]

       ...

       count_reg_n_0[6]

 

Any clues?

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Xilinx Employee
Xilinx Employee
12,034 Views
Registered: ‎07-21-2014

HI,

Can you please share the testcase?

-Shreyas
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Xilinx Employee
Xilinx Employee
11,915 Views
Registered: ‎05-20-2015

Hi @space_boy,

 

Can you please attach the synthesis log here?

 

-Rajesh

 

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Moderator
Moderator
11,883 Views
Registered: ‎07-21-2014

Hi @space_boy,

 

It depends upon your assignments and usage of the count signals. Make sure you have valid connections for these signals. VSS must be throwing few warnings for these signals before removing. Give DONT_TOUCH property to these signals and check connection after synthesis and observe whether the connectivity is valid or not.

 

We need to look into the RTL code to comment on this behaviour.

 

Thanks,
Anusheel
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Participant
Participant
11,855 Views
Registered: ‎11-21-2007

SOLVED: Thanks for the input and interest in the problem. I found the setting "keep equivalent registers" which, when set, keeps the bits of the register contiguous. Without it, some of the bits were presumably "optimized" into a different arrangement.

 

Ron

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Xilinx Employee
Xilinx Employee
11,324 Views
Registered: ‎07-21-2014

Hi @space_boy,

Please mark the answer as accepted solution to close this thread.

-Shreyas

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