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Observer
Observer
8,380 Views
Registered: ‎02-20-2014

Blackbox mssing from packaged IP

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I get these messages below when running vivado flow in non-project mode....

 

I have regenerated BD after resetting output products as stated in other threads, with no luck.

I see that this thread has another solution:

http://forums.xilinx.com/t5/Implementation/Blackbox-mssing-from-packaged-IP/m-p/435854#M8434

 

...but I cannot find where to uncheck "is include"....does anyone know? Or, do you have any other suggestions?

 

I run Vivado 2014.2 and would prefer not to upgrade now, because I am about to finish a project. I have not seen this error until today. I installed a full license yesterday, have been running on webpack-license earlier.

 

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ERROR: [Opt 31-30] Blackbox u0/system_i/E1FrontEnd_bram_0/e1Data[0]_INST_0 (tricell) is driving pin D of primitive cell u0/system_i/E1FrontEnd_bram_0/U0/ProcIfController_1/dataFromE1Dev_reg[0]. This blackbox cannot be found in the existing library.
Resolution: Please check the input design and ensure that the specific blackbox module is defined. Once the design is modified, then re-run the Vivado flow.
ERROR: [Opt 31-30] Blackbox u0/system_i/E1FrontEnd_bram_0/e1Data[1]_INST_0 (tricell) is driving pin D of primitive cell u0/system_i/E1FrontEnd_bram_0/U0/ProcIfController_1/dataFromE1Dev_reg[1]. This blackbox cannot be found in the existing library.
Resolution: Please check the input design and ensure that the specific blackbox module is defined. Once the design is modified, then re-run the Vivado flow.
ERROR: [Opt 31-30] Blackbox u0/system_i/E1FrontEnd_bram_0/e1Data[2]_INST_0 (tricell) is driving pin D of primitive cell u0/system_i/E1FrontEnd_bram_0/U0/ProcIfController_1/dataFromE1Dev_reg[2]. This blackbox cannot be found in the existing library.
Resolution: Please check the input design and ensure that the specific blackbox module is defined. Once the design is modified, then re-run the Vivado flow.
ERROR: [Opt 31-30] Blackbox u0/system_i/E1FrontEnd_bram_0/e1Data[3]_INST_0 (tricell) is driving pin D of primitive cell u0/system_i/E1FrontEnd_bram_0/U0/ProcIfController_1/dataFromE1Dev_reg[3]. This blackbox cannot be found in the existing library.
Resolution: Please check the input design and ensure that the specific blackbox module is defined. Once the design is modified, then re-run the Vivado flow.
ERROR: [Opt 31-30] Blackbox u0/system_i/E1FrontEnd_bram_0/e1Data[4]_INST_0 (tricell) is driving pin D of primitive cell u0/system_i/E1FrontEnd_bram_0/U0/ProcIfController_1/dataFromE1Dev_reg[4]. This blackbox cannot be found in the existing library.
Resolution: Please check the input design and ensure that the specific blackbox module is defined. Once the design is modified, then re-run the Vivado flow.
ERROR: [Opt 31-30] Blackbox u0/system_i/E1FrontEnd_bram_0/e1Data[5]_INST_0 (tricell) is driving pin D of primitive cell u0/system_i/E1FrontEnd_bram_0/U0/ProcIfController_1/dataFromE1Dev_reg[5]. This blackbox cannot be found in the existing library.
Resolution: Please check the input design and ensure that the specific blackbox module is defined. Once the design is modified, then re-run the Vivado flow.
ERROR: [Opt 31-30] Blackbox u0/system_i/E1FrontEnd_bram_0/e1Data[6]_INST_0 (tricell) is driving pin D of primitive cell u0/system_i/E1FrontEnd_bram_0/U0/ProcIfController_1/dataFromE1Dev_reg[6]. This blackbox cannot be found in the existing library.
Resolution: Please check the input design and ensure that the specific blackbox module is defined. Once the design is modified, then re-run the Vivado flow.
ERROR: [Opt 31-30] Blackbox u0/system_i/E1FrontEnd_bram_0/e1Data[7]_INST_0 (tricell) is driving pin D of primitive cell u0/system_i/E1FrontEnd_bram_0/U0/ProcIfController_1/dataFromE1Dev_reg[7]. This blackbox cannot be found in the existing library.
Resolution: Please check the input design and ensure that the specific blackbox module is defined. Once the design is modified, then re-run the Vivado flow.
INFO: [Opt 31-11] Eliminated 194 unconnected cells.

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Observer
Observer
15,078 Views
Registered: ‎02-20-2014

Solved by upgrading to 2014.4...

 

Synthesis-tool gives correct result.

View solution in original post

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Xilinx Employee
Xilinx Employee
8,374 Views
Registered: ‎02-16-2014

Hi,

 

You can find this Is Include option during packaging the IP.

 

Check below snapshot.

packager.PNG

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Observer
Observer
15,079 Views
Registered: ‎02-20-2014

Solved by upgrading to 2014.4...

 

Synthesis-tool gives correct result.

View solution in original post

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