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Explorer
Explorer
533 Views
Registered: ‎09-08-2009

Block Ram always infers TDP problem

 

After implementation finished, when I check cell properties of the implemented BMEM: RAM_MODE is always TDP(attached), why can't I make it SDP

  • If I use TDP template and connect the unused read and write ports to 0 on top module
  • If I use SDP template 
  • If I use SDP template + use RAM_MODE = SDP attribute
  • if I make single port ROM (no write port)

PS: I am inferring by just a VHDL code using Xilinx templates. (No primitive instantiation, No IP Core Usage), For both Data Width 16 and 32 tested, Depth 1024

PS2: Synthesize shows Port A is used for Write and Port B is used for Read (attached)

 

 

always_tdp.png
portA_portB_WR.PNG
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Xilinx Employee
Xilinx Employee
452 Views
Registered: ‎06-04-2020

I'm not sure what template you are using but there are XPM (Xilinx Paramerterized Macros) templates available. One of which is the SDP. You can find these memory macros in Vivado under Tools > Language Templates and the search on xpm_mem.

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Xilinx Employee
Xilinx Employee
426 Views
Registered: ‎05-14-2008

  • If I use SDP template 
  • If I use SDP template + use RAM_MODE = SDP attribute

Can you elaborate what you mean by the above two items?

If you're using an SDP tepmlate that Xilinx user guide or language template provides, can you post your code so that we can try if we also get TDP?

-vivian

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Explorer
Explorer
363 Views
Registered: ‎09-08-2009

@viviany @GBS 

I was able to achieve inferring SDP, when I change the data size to 64. With the same source code when the data size is 64 or 32 it infers different SDP or TDP

PS: I was using the same template as Vivado-> Tools-> Language Templates.

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Xilinx Employee
Xilinx Employee
335 Views
Registered: ‎05-14-2008

Would you explicitely specify which template you're using that 64 bit and 32 bit data size gave different SDP or TDP results?

OR would you attatch the code you're using?

-vivian

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