06-18-2020 05:01 AM - edited 06-18-2020 05:15 AM
After implementation finished, when I check cell properties of the implemented BMEM: RAM_MODE is always TDP(attached), why can't I make it SDP
PS: I am inferring by just a VHDL code using Xilinx templates. (No primitive instantiation, No IP Core Usage), For both Data Width 16 and 32 tested, Depth 1024
PS2: Synthesize shows Port A is used for Write and Port B is used for Read (attached)
06-22-2020 06:13 AM
I'm not sure what template you are using but there are XPM (Xilinx Paramerterized Macros) templates available. One of which is the SDP. You can find these memory macros in Vivado under Tools > Language Templates and the search on xpm_mem.
06-23-2020 03:12 AM
Can you elaborate what you mean by the above two items?
If you're using an SDP tepmlate that Xilinx user guide or language template provides, can you post your code so that we can try if we also get TDP?
07-03-2020 04:03 AM
07-05-2020 07:55 PM
Would you explicitely specify which template you're using that 64 bit and 32 bit data size gave different SDP or TDP results?
OR would you attatch the code you're using?