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tim_severance
Scholar
Scholar
2,306 Views
Registered: ‎03-03-2017

Block design named port connection does not exist in block design wrapper

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I am using Vivado 2017.4 and upgraded a design that was previously fully synthesizing and implementing successfully in 2017.2.1.   I went through the proper routes of reporting IP status, upgrading IP, resetting block design output products, generating block design output products, creating HDL wrapper managed by Vivado and then started synthesis.

 

Synthesis fails with the errors shown below in Figure 1.   What is strange is that looking through the wrapper (Figure 2) you can clearly see that the ports are indeed there.   The top level instantiation is shown in Figure 3.   Does anybody have any idea what might be going on?

 

Figure 1:

vivado1.png

 

Figure 2:

Vivado2.png

 

Figure 3:

Vivado3.png

 

Thanks.

Tim

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prathikm
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2,745 Views
Registered: ‎09-15-2016

Hi @tim_severance,

 

Can you try changing the *iic to *IIC? or is there a wire declared?

 

Regards,
Prathik
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prathikm
Moderator
Moderator
2,746 Views
Registered: ‎09-15-2016

Hi @tim_severance,

 

Can you try changing the *iic to *IIC? or is there a wire declared?

 

Regards,
Prathik
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tim_severance
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Registered: ‎03-03-2017

@prathikm,

   Thanks.   Dumb mistake.   That fixed it.

Tim

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