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Visitor
Visitor
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Registered: ‎09-18-2018

Blockram with Procedures

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I'm trying the following code, as to make some other tricks and creating some libraries, but it seems it cannot infer a block ram.

library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;

entity dp_ram is
    port (
      --general
      clk_i   : in  std_logic;
      addr_i  : in  std_logic_vector(7 downto 0);
      data_i  : in  std_logic_vector(7 downto 0);
      data_o  : out std_logic_vector(7 downto 0);
      we_i    : in  std_logic
    );
end dp_ram;

architecture behavioral of dp_ram is

  type ram_data_t  is array (255 downto 0) of std_logic_vector(data_i'range);
  signal ram_data_s : ram_data_t := (others=>(others=>'0'));

  function read_ram_p (addr : std_logic_vector; ram : ram_data_t) return std_logic_vector is
  begin
    return ram(to_integer(unsigned(addr)));
  end read_ram_p;

  procedure write_ram_p (signal data : in std_logic_vector; signal we : in std_logic; signal addr : in std_logic_vector; signal ram : inout ram_data_t) is
  begin
    ram <= ram;
    if we = '1' then
      ram(to_integer(unsigned(addr))) <= data;
    end if;
  end write_ram_p;

begin

  process(clk_i)
    begin
      if rising_edge(clk_i) then
        dataa_o <= read_ram(addr_i,ram_s);
        write_ram_p(ram_data_s,addr_i,data_i,we_i);
      end if;
    end process;


end behavioral;

 

The goal is to create blockram from procedures (or protected types in the future).

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Xilinx Employee
Xilinx Employee
339 Views
Registered: ‎05-14-2008

Section "RAM HDL Coding Guidelines" in UG901 provides many VHDL templates to infer Block RAM.

You can compare yours with the examples.

-vivian

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Xilinx Employee
Xilinx Employee
340 Views
Registered: ‎05-14-2008

Section "RAM HDL Coding Guidelines" in UG901 provides many VHDL templates to infer Block RAM.

You can compare yours with the examples.

-vivian

-------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
-------------------------------------------------------------------------------------------------

View solution in original post

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Visitor
Visitor
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Registered: ‎09-18-2018

Thanks for the reply.

I just want to keep it here, so if someone tries they will know it cannot be done.

Also, reminds Xilinx that it would be nice to be possible to do it.

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