I'm trying the following code, as to make some other tricks and creating some libraries, but it seems it cannot infer a block ram.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dp_ram is
port (
--general
clk_i : in std_logic;
addr_i : in std_logic_vector(7 downto 0);
data_i : in std_logic_vector(7 downto 0);
data_o : out std_logic_vector(7 downto 0);
we_i : in std_logic
);
end dp_ram;
architecture behavioral of dp_ram is
type ram_data_t is array (255 downto 0) of std_logic_vector(data_i'range);
signal ram_data_s : ram_data_t := (others=>(others=>'0'));
function read_ram_p (addr : std_logic_vector; ram : ram_data_t) return std_logic_vector is
begin
return ram(to_integer(unsigned(addr)));
end read_ram_p;
procedure write_ram_p (signal data : in std_logic_vector; signal we : in std_logic; signal addr : in std_logic_vector; signal ram : inout ram_data_t) is
begin
ram <= ram;
if we = '1' then
ram(to_integer(unsigned(addr))) <= data;
end if;
end write_ram_p;
begin
process(clk_i)
begin
if rising_edge(clk_i) then
dataa_o <= read_ram(addr_i,ram_s);
write_ram_p(ram_data_s,addr_i,data_i,we_i);
end if;
end process;
end behavioral;
The goal is to create blockram from procedures (or protected types in the future).
