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Adventurer
Adventurer
266 Views
Registered: ‎11-18-2017

Buffers in a synthesized design.

 

Below figure is the elaborated design.

 

es.JPG

 

 

When I synthesize the design, the synthesized schematic looks like below figure.

 

ss.JPG

 

At the input, 2 buffers(IBUF) appeared. I don't know why these buffers appeared even though I didn't added in my VHDL code.

Why do I need these buffers and why does the synthesizers added these buffers? Can't just inputs go directly into the LUT?

Thanks for your help.

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1 Reply
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Moderator
Moderator
264 Views
Registered: ‎01-16-2013

Re: Buffers in a synthesized design.

@kimjaewon

 

These are Input buffers which are automatically added by synthesis. Signals used as inputs to 7 series devices must use an input buffer (IBUF).

Check this link:

https://forums.xilinx.com/t5/General-Technical-Discussion/What-s-the-necessity-to-use-ibuf-component/td-p/139442

 

--SYed

 

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