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Contributor
Contributor
7,990 Views
Registered: ‎12-29-2013

Bugs in Vivado 2014.1

I've reported a couple of Vivado and Xsim 2013.4 bugs in december 2013. I've now tested with Vivado 2014.1 and my test cases still fail, some with slightly different errors:

 

http://forums.xilinx.com/t5/Synthesis/Strange-output-const-zero-bug-with-Vivado-gt-gt-gt-signedness/td-p/401411

 

Does not return constant 0 anymore. But sign extension is done incorrectly. It shopuld return 1111 for a=1 and b=0 but returns 0001 instead.

 

http://forums.xilinx.com/t5/Synthesis/Vivado-creates-netlist-with-inputs-shorted-together/td-p/397161

 

Does not short together the inputs anymore but still returns an invalid circuit. For example a=63 and b=15 yields y0=7, but y0 should obviously be set to constant 0.

 

http://forums.xilinx.com/t5/Synthesis/Vivado-GDpGen-implementDivMod-DFNode-bool-Assertion-TBD-failed/td-p/401721

 

Still fails with the same assert.

 

http://forums.xilinx.com/t5/Synthesis/Vivado-bug-in-undef-handling-for-relational-operators/td-p/403469

 

Still same faulty behavior.

 

http://forums.xilinx.com/t5/Simulation-and-Verification/Bug-in-XSIM-when-combining-reduce-op-and-signed-unsigned/td-p/406801

 

Still same faulty behavior.

 

http://forums.xilinx.com/t5/Simulation-and-Verification/XSim-implements-0-1-incorrectly/td-p/406517

 

Still same faulty behavior.

 

http://forums.xilinx.com/t5/Simulation-and-Verification/XSim-hangs-on-power-operations-with-large-exponents/td-p/406887

 

Still same faulty behavior.

 

What is the status of those? When can I expect fixes? I have more bug reports pending but are holding back on reporting them until the ones I already reported are fixed so I don't send in duplicates.

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Xilinx Employee
Xilinx Employee
7,969 Views
Registered: ‎07-01-2010

Hi Clifford,

 

I will re-look at the posts and will update you on them.

 

Regards,

Achutha

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Xilinx Employee
Xilinx Employee
7,842 Views
Registered: ‎07-01-2010

Hi Clifford,

I have looked at the synthesis bug reported and i see they are not completely fixed.I am currently checking for the CR details.

I am also following up with the simulation bug.

I will keep you posted.

Regards,
Achutha
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Xilinx Employee
Xilinx Employee
7,815 Views
Registered: ‎07-01-2010

Hi Clifford,

 

The simulation posts will taken care by simulation moderator and will be updated in the respective posts.

 

Still same faulty behavior.

 

http://forums.xilinx.com/t5/Simulation-and-Verification/Bug-in-XSIM-when-combining-reduce-op-and-sig...

 

Still same faulty behavior.

 

http://forums.xilinx.com/t5/Simulation-and-Verification/XSim-implements-0-1-incorrectly/td-p/406517

 

Still same faulty behavior.

 

http://forums.xilinx.com/t5/Simulation-and-Verification/XSim-hangs-on-power-operations-with-large-ex...

 

Regards,

Achutha

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Scholar
Scholar
7,551 Views
Registered: ‎06-14-2012

Hi Clifford

Thanks for sharing your feedback and reporting this to us.Xilinx is committed to any bugs or feedback reported.

 

We are actively following on these posts so that we could share updates or file bugs if they havent been done yet.

 

Regards

Sikta

 

 

 

 

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Xilinx Employee
Xilinx Employee
7,535 Views
Registered: ‎07-01-2010

Hi Clifford,

 

Summary/status of the synthesis issue posted :

 

Issue:1

http://forums.xilinx.com/t5/Synthesis/Strange-output-const-zero-bug-with-Vivado-gt-gt-gt-signedness/...

 

CR filed: CR#799204 

Current Status: set for a fix in 2014.3

 

Issue:2

http://forums.xilinx.com/t5/Synthesis/Vivado-creates-netlist-with-inputs-shorted-together/td-p/39716...

CR filed :CR#799205

Current status:Set  for a fix in 2014.3

 

Issue:3

 

http://forums.xilinx.com/t5/Synthesis/Vivado-GDpGen-implementDivMod-DFNode-bool-Assertion-TBD-failed...

 

Issue fixed in 2014.2 latest build.

 

Issue:4 

http://forums.xilinx.com/t5/Synthesis/Vivado-bug-in-undef-handling-for-relational-operators/td-p/403...

 

Issue fixed in 2014.2 latest build.

 

Regards,

Achutha

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