04-16-2014 03:59 AM
I've reported a couple of Vivado and Xsim 2013.4 bugs in december 2013. I've now tested with Vivado 2014.1 and my test cases still fail, some with slightly different errors:
Does not return constant 0 anymore. But sign extension is done incorrectly. It shopuld return 1111 for a=1 and b=0 but returns 0001 instead.
Does not short together the inputs anymore but still returns an invalid circuit. For example a=63 and b=15 yields y0=7, but y0 should obviously be set to constant 0.
Still fails with the same assert.
Still same faulty behavior.
Still same faulty behavior.
http://forums.xilinx.com/t5/Simulation-and-Verification/XSim-implements-0-1-incorrectly/td-p/406517
Still same faulty behavior.
Still same faulty behavior.
What is the status of those? When can I expect fixes? I have more bug reports pending but are holding back on reporting them until the ones I already reported are fixed so I don't send in duplicates.
04-16-2014 05:00 AM
Hi Clifford,
I will re-look at the posts and will update you on them.
Regards,
Achutha
04-20-2014 11:38 PM
04-21-2014 11:25 PM
Hi Clifford,
The simulation posts will taken care by simulation moderator and will be updated in the respective posts.
Still same faulty behavior.
Still same faulty behavior.
http://forums.xilinx.com/t5/Simulation-and-Verification/XSim-implements-0-1-incorrectly/td-p/406517
Still same faulty behavior.
Regards,
Achutha
05-19-2014 02:29 PM
Hi Clifford
Thanks for sharing your feedback and reporting this to us.Xilinx is committed to any bugs or feedback reported.
We are actively following on these posts so that we could share updates or file bugs if they havent been done yet.
Regards
Sikta
05-20-2014 07:00 AM
Hi Clifford,
Summary/status of the synthesis issue posted :
Issue:1
CR filed: CR#799204
Current Status: set for a fix in 2014.3
Issue:2
CR filed :CR#799205
Current status:Set for a fix in 2014.3
Issue:3
Issue fixed in 2014.2 latest build.
Issue:4
Issue fixed in 2014.2 latest build.
Regards,
Achutha