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chinn29393
Visitor
Visitor
2,451 Views
Registered: ‎07-17-2017

Building Delay elements using LUT

Hi All,

 

I want to delay my input signal lesser than my clock period 5ns(200 MHz).

Can we build delay elements using LUT?

Is there any way to simulate the same?

 

Thanks in advance!

 

Regards,

Chinna Thambi M. 

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4 Replies
arpansur
Moderator
Moderator
2,441 Views
Registered: ‎07-01-2015

Hi @chinn29393,

 

Which device you are using?

You can use IDELAY to delay the i/p signal.

 

 

Thanks,
Arpan
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chinn29393
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Registered: ‎07-17-2017

Hi Arpan,

 

Thanks for the reply,

I am using Vitrex 5 (xc5vsx95t-2ff1136) FPGA.

I am already using IDELAY component for input delay of upto 4.914 ns(tap values from 0 to 63) with 200 MHz delay clock.

I require a delay more than 4.914ns. But i do not want to add delays by adding an FD.

My input is asynchronous to the clock so I do not want to sample it with the clock(200MHz) and lead to an uncertainty of 5ns.

So I am looking to create LUT based delay element.

I need your guidance on that.

Sorry if my previous question was misleading.

 

Thanks and Regards,

Chinna Thambi M. 

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chinn29393
Visitor
Visitor
2,276 Views
Registered: ‎07-17-2017

Hoping some one could help for my previous query

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muzaffer
Teacher
Teacher
2,220 Views
Registered: ‎03-31-2012

@chinn29393 any delay built with LUTs will be subject to PVT variations and not give you satisfactory results. Are you sure you can't cascade IDELAY cells to get more delay. Even though this still involves some fabric routing (ie not fully calibrated), the results will still be better than LUT delays. 

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