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CR Request: Update UG901 Vivado Synthesis User Guide to document supported VHDL and Verilog language constructs

CR Request: Update UG901 Vivado Synthesis User Guide to document supported VHDL and Verilog language constructs

 

[Posting this to the forums as I no longer have WebCase access from this account.]

 

This is a follow up to my earlier posts from July 2013 and January 2014:

http://forums.xilinx.com/t5/Synthesis/Vivado-Synthesis-support-for-IEEE-ieee-proposed-Fixed-Point/m-p/336255#M8555

 

"However, even more annoying than the outdated Answer Records is the complete omission of the VHDL/Verilog "supported language constructs" chapters from the UG901 Vivado Synthesis User Manual."

 

"This is your flagship synthesis product, nearly two years after launch, and the documentation is still missing fundamental information needed to actually use the tool."

 

After encountering yet another Vivado synthesis issue tonight, I searched the latest Vivado 2014.1 Synthesis User Guide and discovered that these basic problems remain uncorrected, nearly a year after I first pointed them out.

 

-Brian

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Hi Brian,

Thanks for sharing the feedback.
I don't think we will be able to list all the constructs supported but will try to see update the AR's and the UG901.

Regards,
Achutha
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Achutha,

>

> I don't think we will be able to list all the constructs supported

>

Then please explain exactly how Xilinx expects us to be able to write code for a synthesis tool which has absolutely no documentation of supported VHDL and Verilog language constructs?

 

[ And even worse than writing new RTL code for Vivado is porting existing code that ***works in XST*** but silently fails in Vivado ]

 

The time for Xilinx to have written this section of the manual was two years ago at Vivado product launch.

 

The present UG901 contains such a chapter for SystemVerilog, but the continuing and conspicuous absence of this vital information for VHDL and Verilog, at this late date, is both inexplicable and inexcusable.

 

-Brian

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@achutha wrote:
Hi Brian,

Thanks for sharing the feedback.
I don't think we will be able to list all the constructs supported but will try to see update the AR's and the UG901.


Let me be blunt.

 

Why the hell not? The number of constructs is finite and the languages are not all that complex.

 

Put another way: your competitors document the language constructs which they do and do not support.

 

 

----------------------------Yes, I do this for a living.
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@brimdavis wrote:

[ And even worse than writing new RTL code for Vivado is porting existing code that ***works in XST*** but silently fails in Vivado ]


-Brian


 

Hi Brian,

 

I think that for 99% of the cases -except where we see that XST generated bad or suboptimal logic- we guarantee support for all constructs that XST supported.

 

Can you give examples or share testcase for which we can file CRs?

(FYI - a lot of engineering development was done on improving Vivado synthesis the last few releases)

 

 

Best regards,

Dries

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@brimdavis wrote:

CR Request: Update UG901 Vivado Synthesis User Guide to document supported VHDL and Verilog language constructs

 

[Posting this to the forums as I no longer have WebCase access from this account.]

 

This is a follow up to my earlier posts from July 2013 and January 2014:

http://forums.xilinx.com/t5/Synthesis/Vivado-Synthesis-support-for-IEEE-ieee-proposed-Fixed-Point/m-p/336255#M8555

 

"However, even more annoying than the outdated Answer Records is the complete omission of the VHDL/Verilog "supported language constructs" chapters from the UG901 Vivado Synthesis User Manual."

 

"This is your flagship synthesis product, nearly two years after launch, and the documentation is still missing fundamental information needed to actually use the tool."

 

After encountering yet another Vivado synthesis issue tonight, I searched the latest Vivado 2014.1 Synthesis User Guide and discovered that these basic problems remain uncorrected, nearly a year after I first pointed them out.

 

-Brian


Hi Brian,

 

thank you for your honest and open feedback.

what are you specifically looking for?

A list as it was available in the XST user guide?

Or could you give a reference to what you had in mind?

 

I don't know for sure, but I think we didn't add this information but instead wanted to make it available there where you need it: inside Vivado.

Have you looked at the Language Templates in Vivado? Or is this not what you are looking for?

 

Lastly, have you noticed the feedback link on the bottom of every page in our documentation?

screenshot_002.jpg

I would recommend to send this feedback through there because I think that goes directly to the authors and is the recommended flow for passing on feedback about our documentation.

 

 

Thanks!

Dries

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driesd wrote:

what are you specifically looking for?

A list as it was available in the XST user guide?


Yes, exactly. Chapter 3 of the XST User Guide for V6, S6 and 7 Series Devices (UG687) is comprehensive. Please, review it.


I don't know for sure, but I think we didn't add this information but instead wanted to make it available there where you need it: inside Vivado.


Well, it's not inside Vivado, as far as I can tell. It seems to me that UG901, Vivado Design Suite User Guide: Synthesis, is where language support details should be, since it seems to be the Vivado version of UG687.


Have you looked at the Language Templates in Vivado? Or is this not what you are looking for?


The list of Language Templates is a separate issue. They show how one should write code which implements various logic structures. They say nothing about whether certain language features are supported, you know, types, attributes, operands, generates and configurations, etc etc.

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driesd wrote:

 

Lastly, have you noticed the feedback link on the bottom of every page in our documentation?

screenshot_002.jpg

I would recommend to send this feedback through there because I think that goes directly to the authors and is the recommended flow for passing on feedback about our documentation.


Done.

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Dries,

[ note: bassman59's earlier post says the following more succinctly, but since I'd already typed up this response... ]

>
> what are you specifically looking for?
> A list as it was available in the XST user guide?
>
A ***CHAPTER***, or more, for each language, as was available in the XST user guide[1].

>
> Have you looked at the Language Templates in Vivado? Or is this not what you are looking for?
>
I am ***NOT*** looking for cookie-cutter "Language Templates" to cut and paste into code.

I am looking for a detailed specification of what language constructs, and IEEE packages, are supported by the tool.

This information ***WAS*** provided, for both VHDL and Verilog, in the XST Users's guide for the ISE tool suite.

>
> I don't know for sure, but I think we didn't add this information but
> instead wanted to make it available there where you need it: inside Vivado.
>
This theory of yours self-destructs when confronted with the existence[2] of a SystemVerilog "supported language constructs" chapter in UG901.

But this exists in Vivado only for SystemVerilog, and not for VHDL or plain-old-Verilog, as I have mentioned in my previous posts.

>
> Lastly, have you noticed the feedback link on the bottom of every page in our documentation?
>
This is not a simple documentation error to report.

I would think a CR far more appropriate for a fundamental ***LACK*** of documentation such as this.

The Xilinx Synthesis engineering folks ( or the company to which Xilinx is outsourcing the Synthesis flow ) needs to provide your documentation folks with the detailed language specification compliance matrix required to write such chapters.

If Xilinx is developing Vivado Synthesis without such a language compliance matrix, we are all doomed.


-Brian

-----------------------
[1] UG687 (v14.5) XST User Guide for Virtex-6,Spartan-6, and 7 Series Devices
http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/xst_v6s6.pdf

"Chapter 3 VHDL Support"             pages 23-75
"Chapter 4 Verilog Support"          pages 77-101
"Chapter 5 Behavioral Verilog"       pages 103-124
"Chapter 6 Mixed Language Support"   pages 127-132

-----------------------
[2] UG901 (v2014.1) Vivado Synthesis User Guide
http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_1/ug901-vivado-synthesis.pdf

Quoting from page 13:
"
" The Vivado synthesis tool reads the subset of files that can be
" synthesized in VHDL, Verilog, or SystemVerilog options supported
" in the Xilinx tools. Chapter 3, SystemVerilog Support, provides
" details on the supported SystemVerilog constructs.
"

"Chapter 3: SystemVerilog Support"  pages 54-65

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Hi All,

Thanks for all your inputs/ feedback on the user guide.

I am one of the reviewers for UG901, i will pass on this information to the team and will try to see the document is updated.

Regards,
Achutha
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@achutha wrote:
and will try to see the document is updated.


"There is no try. There is do, and do not."

  --- Yoda

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Hi Yoda :)

 

it is definitely on our radar.

 

Unfortunately currently there simply aren't enough resources to add these chapters. We decided to rather focus on features and quality first.

SystemVerilog had it's own information because it is a newly covered language.

As a priority we will add some mixed language information in the next revision of the guide in 2014.3.

 

 

Best regards,

Dries

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@driesd wrote:

Unfortunately currently there simply aren't enough resources to add these chapters. We decided to rather focus on features and quality first.


Famous usability statement: "If it's not documented, the feature DOES NOT EXIST." Claiming that a multi-billion-dollar corporation doesn't have the resources to properly document their flagship design tool is, quite frankly, horse**bleep**.


SystemVerilog had it's own information because it is a newly covered language.


Nobody cares about SystemVerilog.


As a priority we will add some mixed language information in the next revision of the guide in 2014.3.


Nobody cares about mixed language information. Just replicate the aforementioned sections of the XST user guide, modified so it tells us what Vivado supports.

 

You must already have that information in-house somewhere. Have a student intern correlate that information, format it like the XST guide, and push it out already.

 

Let's recap:

 

* Tools that support non-Series-7 devices will never run on the most recent version of the standard operating system.

* Tools that do run on that operating system aren't fully documented, so the users cannot migrate code for non-supported devices to possibly-available new devices without possibly running into a minefield of language support issues.

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@brimdavis wrote:

CR Request: Update UG901 Vivado Synthesis User Guide to document supported VHDL and Verilog language constructs

 

[Posting this to the forums as I no longer have WebCase access from this account.]


it is now Webcase 

1007631

I'm sure it's been routed to /dev/null already.

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Dries,
>
> I think that for 99% of the cases -except where we see that XST generated bad

> or suboptimal logic- we guarantee support for all constructs that XST supported.
>
That has not been my experience.

>
> Can you give examples or share testcase for which we can file CRs?
>
IIRC in older Vivado releases I've seen VHDL issues with:
 - package and library namespaces seem to be fundamentally broken
 - silent "INFO: [Synth 8-2943]" failures with code that synthesizes correctly in XST
 - problems with functions in packages
 - problems with records
 - problems with indexed vector subscripts
 - problems with unconstrained vector ports

I can attempt to post simplified testcases here as I encounter problems with 2014.1

But frankly, given Xilinx's track record at responding to Vivado Synthesis bug posts in the forums, I have trouble working up any sort of enthusiasm for such an effort.

>
> (FYI - a lot of engineering development was done on improving Vivado synthesis the last few releases)
>
What exactly might these improvements be ?

And where might they be documented ?

There is a brief list on page 11 of the UG973 (v2014.1) Vivado release notes, but not, to my reading, anything suggesting major improvements to synthesis language support.

-Brian

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bassman59 wrote:

>

> Famous usability statement: "If it's not documented, the feature DOES NOT EXIST."

> Claiming that a multi-billion-dollar corporation doesn't have the resources to properly

> document their flagship design tool is, quite frankly, horse**bleep**.

>

Exactly!!! Thanks for sparing me from more typing, and for getting a Webcase filed.

 

>

> * Tools that do run on that operating system aren't fully documented,

>

Nor fully tested, nor actually quite finished yet...

 

-Brian

 

 

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@brimdavis wrote:

 

I can attempt to post simplified testcases here as I encounter problems with 2014.1

But frankly, given Xilinx's track record at responding to Vivado Synthesis bug posts in the forums, I have trouble working up any sort of enthusiasm for such an effort.

>
> (FYI - a lot of engineering development was done on improving Vivado synthesis the last few releases)
>
What exactly might these improvements be ?

And where might they be documented ?

There is a brief list on page 11 of the UG973 (v2014.1) Vivado release notes, but not, to my reading, anything suggesting major improvements to synthesis language support.

-Brian


Hi Brian,

 

I'm ashamed regarding this example post. Rest assured: I will discuss fixing reported bugs from the forum with management whenever I get the opportunity.

Either we should bluntly say we will never fix or either we should fix it, but nothing in between.

 

In general, I think we do our best to listen and improve.

I'm with Xilinx now for 8 years and when I compare ISE with Vivado, I see much faster resolution of bugs than with ISE.

 

Regarding documentation of improvements: these are typically documented in the answer record database.

See this master answer record for 2013.x: http://www.xilinx.com/support/answers/55334.htm

 

 

Best regards

Dries

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@brimdavis wrote:

@bassman59 wrote:

>

> Famous usability statement: "If it's not documented, the feature DOES NOT EXIST."

> Claiming that a multi-billion-dollar corporation doesn't have the resources to properly

> document their flagship design tool is, quite frankly, horse**bleep**.

>

Exactly!!! Thanks for sparing me from more typing, and for getting a Webcase filed.

 

>

> * Tools that do run on that operating system aren't fully documented,

>

Nor fully tested, nor actually quite finished yet...

 

-Brian

 

 


Hi Brian,

 

again, no excuse: we don't say we won't document it. It's just not the highest priority right now.

In general, I can state that we support everything from the VHDL and Verilog LRM. In some special cases, we compare with XST and competition (Synplify, ...)

 

Regarding fully tested: we run hundreds if not thousands of testcases on a daily basis to verify correct behaviour and we run formal verification to verify correct logic is generated.

The problem is that Vivado is a completely new tool and was built from the ground up. Compared to synthesis, the back-end place and route tools are easy.

Synthesis is simply exponentially more difficult due to the wide variaty of constructs and combinations of constructs and logic.

Maybe we underestimated the effort. We did our best. I've migrated many customers to Vivado and I can honestly say that even for the largest, most complex projects with hundreds of HDL files, I've rarely seen synthesis issues. However, I've only seen maybe 50 projects with 50 different styles of writing code. Xilinx has I believe 30.000 customers...no wonder that from time to time new issues pop up. It all depends on the style of coding.

 

Regarding finished: I don't think we're there yet, but I've seen massive improvements in the last few releases 2013.x - 2014.1. Just give us a little bit more time, I'm convinced we will get there!

 

 

Best regards

Dries

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@brimdavis wrote:

CR Request: Update UG901 Vivado Synthesis User Guide to document supported VHDL and Verilog language 


Good news, everybody. Webcase #1007631 has been accepted and CR #700944 has been filed.

 

Quote: "It will be fixed in a future release."

 

Of course, "Future release" could mean well after the sun has gone dark, but hey, it's in the system.

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While attempting to document supported VHDL and Verilog Language constructs, I found some old documentation with a link to an FTP site. I would like the files from XST Examples.zip.

Can anyone in Xilinx help me?

Regards,

 

Robbin Rogers, PMP

Xilinx
Senior Staff Writer

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Can you let know the document ID/version and which page the link to the FTP is on?

 

-Vivian

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@robbinr "While attempting to document supported VHDL and Verilog Language constructs, I found some old documentation with a link to an FTP site. I would like the files from XST Examples.zip"

 

This might(?) be the current version of the examples you are looking for:

http://www.xilinx.com/txpatches/pub/documentation/misc/xstug_examples.zip

 

Which has subdirectories corresponding to the "VHDL Support" and "Verilog Support" chapters of the XST user's guide.

 

-Brian

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@bassman59 wrote:

@brimdavis wrote:

CR Request: Update UG901 Vivado Synthesis User Guide to document supported VHDL and Verilog language 


Good news, everybody. Webcase #1007631 has been accepted and CR #700944 has been filed.

 

Quote: "It will be fixed in a future release."

 

Of course, "Future release" could mean well after the sun has gone dark, but hey, it's in the system.


Hi,

 

since version 2014.3, we now have this documented:

chapters.png

 

VHDL_support.png

 

 

Best regards

Dries

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@driesd "since version 2014.3, we now have this documented"

Did you read the new chapters of UG901 before posting this?

If not, please pull up the XST and Vivado manuals[1,2] side by side, and take a look for yourself.

I have reviewed the VHDL chapter of UG901 2014.4 in such a fashion:

   It is a slightly reformatted version of the VHDL chapter from the XST manual.

   With mangled indentation in various places, and newly-introduced typos in others [3-12].

   Most importantly, the ***content*** of this former XST chapter has not been updated to accurately reflect the ***actual*** level of Vivado VHDL language support and limitations.

In short, giving the old XST manual a bad haircut does not merit declaring Vivado's language support 'documented'.

-Brian

Documents referenced:

[1] UG687 (v14.5) : XST User Guide for Virtex-6, Spartan-6, and 7 Series Devices
    http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/xst_v6s6.pdf
    Chapter 3, VHDL Support

[2] UG901 (v2014.4) : Vivado Design Suite User Guide Synthesis
    http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_4/ug901-vivado-synthesis.pdf
    Chapter 4, VHDL Support


A few of the many reformatting-incurred problems with UG901 (v2014.4) Chapter 4 :

[3] general : Removal of bulletized lists and hyperlinked section summaries makes the Vivado version harder to read.

[4]  pg 145 : "VHDL Integer Types" mangled by removal of bullets and VHDL->English translation of example code fragment. (see XST manual)

[5]  pg 148 : "Operators" section is now missing link to table 4-11's "VHDL Operators"

[6]  pg 161 : Indentation of code examples has been broken (see XST manual). [One of many instances]

[7]  pg 164 : "Clock Event Statements" rising_edge(clk) / falling_edge(clk) code examples have gone missing (see XST manual)

[8]  pg 165 : "VHDL Initial Values and Operational Set/Reset" section suffers from incomplete de-bulletization.
              The "external data file" phrase should not subsume the following bullet points (see XST manual)

[9]  pg 171 : "VHDL IEEE Packages" horribly mangled indentation renders this section unusable (see XST manual)
              Content needs refresh for current IEEE (numeric_std, numeric_std_unsigned, etc.) vs. obsolete Synopsys packages

[10] pg 174 : XST manual sections "VHDL File Type Support" and "VHDL File Read and File Write Capability" were deleted.
              Why? If textio is not supported in Vivado, absence should be explicitly noted as per first sentence of Chapter 4.

[11] pg 174 : Table 4-11 : merging over a dozen separate XST sections and tables into this single table is tough to read.

[12] pg 176 : the MOD/REM descriptions are likely missing a trailing "of 2"

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Brimdavis,

 

I understand you concern and i acknowledge the differences between XST and Vivado synthesis user guides.

I have divided your comments in sections:

Formatting:

[3] general : Removal of bulletized lists and hyperlinked section summaries makes the Vivado version harder to read.
[4]  pg 145 : "VHDL Integer Types" mangled by removal of bullets and VHDL->English translation of example code fragment. (see XST manual)
[6]  pg 161 : Indentation of code examples has been broken (see XST manual). [One of many instances]

[8]  pg 165 : "VHDL Initial Values and Operational Set/Reset" section suffers from incomplete de-bulletization.
              The "external data file" phrase should not subsume the following bullet points (see XST manual)

[11] pg 174 : Table 4-11 : merging over a dozen separate XST sections and tables into this single table is tough to read.

[7]  pg 164 : "Clock Event Statements" rising_edge(clk) / falling_edge(clk) code examples have gone missing (see XST manual)
[9]  pg 171 : "VHDL IEEE Packages" horribly mangled indentation renders this section unusable (see XST manual)
              Content needs refresh for current IEEE (numeric_std, numeric_std_unsigned, etc.) vs. obsolete Synopsys packages

 

Achutha: I would suggest not to compare between user guides(XST and Vivado) in terms of formatting.I will pass on your inputs to the doc team and see if this can be incorporated.

 

 

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No-Correction Needed:
[12] pg 176 : the MOD/REM descriptions are likely missing a trailing "of 2"

Achutha:On MOD/REM, i have tested this in vivado and this works with constant power so the document is correct.

Please let me know if you have a falling scenario.

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@achutha " I would suggest not to compare between user guides(XST and Vivado) in terms of formatting."

 

 I don't understand what you are trying to say here???

 

 As described in my previous post, the current Vivado guide VHDL chapter *IS* a reformatted copy of the XST chapter.

   My primary complaint is that the content does not reflect actual Vivado language support.

   My secondary complaint is that the reformatting created many problems with the material.

 

Telling me not to compare the formatting does not seem to resolve either of these issues...

 

Looking in more detail at one of the reformatting instances I listed:

[4]  pg 145 : "VHDL Integer Types" mangled by removal of bullets and VHDL->English translation of example code fragment. (see XST manual)

 

Here is the Vivado manual:

"

" For a more compact implementation, define the exact range of

" applicable values. The type MSB is a range of 8 to 15 bits.

"

Which leaves one scratching one's head in puzzlement.

 

Here is the XST manual, with the intended code fragment:

"

" • For a more compact implementation, define the exact range of applicable values.
"       type MSB is range 8 to 15

"

 

-----------------------

"I will pass on your inputs to the doc team and see if this can be incorporated."

 

That list was not comprehensive, but only some examples of the formatting problems.

 

-Brian
 

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@achutha

"On MOD/REM, i have tested this in vivado and this works with constant power so the document is correct."

"Please let me know if you have a falling scenario."

 

My 'likely missing' comment was based not on a testcase, but by noticing the discrepancies in the descriptions of Division,Modulo, and Remainder in the present UG901:

>

>[12] pg 176 : the MOD/REM descriptions are likely missing a trailing "of 2"

>

vivado1.png

 

It seems odd that division would be more restricted than Rem and Mod, does it not?

Perhaps the Division description needs updating.

 

-Brian

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-01-2010

Brian wrote:


 

achutha " I would suggest not to compare between user guides(XST and Vivado) in terms of formatting."

 

 I don't understand what you are trying to say here???

 

 As described in my previous post, the current Vivado guide VHDL chapter *IS* a reformatted copy of the XST chapter.

   My primary complaint is that the content does not reflect actual Vivado language support.

   My secondary complaint is that the reformatting created many problems with the material.

 

Telling me not to compare the formatting does not seem to resolve either of these issues...

 

Here is the Vivado manual:

"

" For a more compact implementation, define the exact range of

" applicable values. The type MSB is a range of 8 to 15 bits.

"

Which leaves one scratching one's head in puzzlement.

 

Here is the XST manual, with the intended code fragment:

"

" • For a more compact implementation, define the exact range of applicable values.
"       type MSB is range 8 to 15


 

I appreciate your effort in pointing the specifics and I agree with you on all your comments on this.

 

I have already recommended the changes suggested by you to the Synthesis Doc team and we are trying to have these incorporated in the 2015.1 release.

 

 

Regards,

Achutha

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