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Scholar dpaul24
Scholar
2,490 Views
Registered: ‎08-07-2014

Can VHDL shared variables be synthesized?

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Please show me how can shared variables be synthesized using Viv2017.4. Can it be done?

I tried it with the "True DualPort Asym Block RAM Write First" and synthesis engine failed.

 

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;


entity asym_ram_tdp is
    generic (
        WIDTHA      : integer := 4;
        SIZEA       : integer := 1024;
        ADDRWIDTHA  : integer := 10;
        WIDTHB      : integer := 16;
        SIZEB       : integer := 256;
        ADDRWIDTHB  : integer := 8 
    );
    port (
        clkA        : in  std_logic;
        clkB        : in  std_logic;
        enA         : in  std_logic;
        enB         : in  std_logic;
        weA         : in  std_logic;
        weB         : in  std_logic;
        addrA       : in  std_logic_vector(ADDRWIDTHA-1 downto 0);
        addrB       : in  std_logic_vector(ADDRWIDTHB-1 downto 0);
        diA         : in  std_logic_vector(WIDTHA-1 downto 0);
        diB         : in  std_logic_vector(WIDTHB-1 downto 0);
        doA         : out std_logic_vector(WIDTHA-1 downto 0);
        doB         : out std_logic_vector(WIDTHB-1 downto 0)
    );
end asym_ram_tdp;


architecture asym_ram_tdp_arc of asym_ram_tdp is

function max(L, R: INTEGER) return INTEGER is
begin
    if L > R then
        return L;
    else
        return R;
    end if;
end;

function min(L, R: INTEGER) return INTEGER is
begin
    if L < R then
        return L;
    else
        return R;
    end if;
end;

function log2 (val: INTEGER) return natural is
    variable res : natural;
begin
    for i in 0 to 31 loop
        if (val <= (2**i)) then
            res := i;
            exit;
        end if;
    end loop;
    return res;
end function Log2;

constant minWIDTH : integer := min(WIDTHA,WIDTHB);
constant maxWIDTH : integer := max(WIDTHA,WIDTHB);
constant maxSIZE  : integer := max(SIZEA,SIZEB);
constant RATIO    : integer := maxWIDTH / minWIDTH;

-- An asymmetric RAM is modeled in a similar way as a symmetric RAM, with an array of array object.
-- Its aspect ratio corresponds to the port with the lower data width (larger depth).
type ramType is array (0 to maxSIZE-1) of std_logic_vector(minWIDTH-1 downto 0);
shared variable my_ram : ramType := (others => (others => '0'));

signal readA  : std_logic_vector(WIDTHA-1 downto 0):= (others => '0');
signal readB  : std_logic_vector(WIDTHB-1 downto 0):= (others => '0');
signal regA   : std_logic_vector(WIDTHA-1 downto 0):= (others => '0');
signal regB   : std_logic_vector(WIDTHB-1 downto 0):= (others => '0');
  
begin

    process (clkA)
    begin
      if rising_edge(clkA) then
        if enA = '1' then
          if weA = '1' then
              my_ram(conv_integer(addrA)) := diA;
              readA <= diA;
          else
              readA <= my_ram(conv_integer(addrA)); 
          end if;
        end if;
        regA <= readA;
      end if;
    end process;
        
    process (clkB)
    begin
      if rising_edge(clkB) then
          for i in 0 to RATIO-1 loop
              if enB = '1' then        
                  if weB = '1' then
                      my_ram(  conv_integer( addrB & conv_std_logic_vector(i,log2(RATIO)) )  ) := diB((i+1)*minWIDTH-1 downto i*minWIDTH);
                  end if;
                  -- The read statement below is placed after the write statement on purpose to ensure write-first synchronization
                  -- through the variable mechanism
                  
                  readB((i+1)*minWIDTH-1 downto i*minWIDTH) <= my_ram(  conv_integer( addrB & conv_std_logic_vector(i,log2(RATIO)) )  );
              end if;
          end loop;
          regB <= readB;
      end if;
    end process;
  
    doA <= regA;
    doB <= regB;

end asym_ram_tdp_arc;

 

Reference posts: https://forums.xilinx.com/t5/Simulation-and-Verification/Speed-up-true-DP-RAM-simulation/td-p/838040

https://forums.xilinx.com/t5/BRAM-FIFO/Why-is-my-asym-DP-BRAM-not-populated/td-p/838441

 

Tagging the relevant persons: @jmcclusk markg@prosensing.com

 

 Anyone from Xilinx?  @hemangd @srimaye@thakurr @shameera

 

 

 

 

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1 Solution

Accepted Solutions
Moderator
Moderator
3,531 Views
Registered: ‎03-16-2017

Re: Can VHDL shared variables be synthesized?

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Hi @dpaul24,

 

Change the type of your .vhd file to VHDL instead of VHDL 2008. (As shown below.)

 

Capt55ure.JPG

 

Regards,

hemangd

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
10 Replies
Moderator
Moderator
2,473 Views
Registered: ‎07-21-2014

Re: Can VHDL shared variables be synthesized?

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@dpaul24

 

Below link shows an example of memory module(page no. 115) which uses shared variable:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug901-vivado-synthesis.pdf

 

Thanks

Anusheel

Thanks
Anusheel
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Explorer
Explorer
2,468 Views
Registered: ‎09-07-2011

Re: Can VHDL shared variables be synthesized?

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Is this a Xilinx ram template?  It spit out a ram in 2016.2 anyways..  haven't check if actually correct.

 

Shared variables (non-protected style) are generally synthesizable just like other variables.

 

What's not working?

 

 

 

 

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Scholar dpaul24
Scholar
2,466 Views
Registered: ‎08-07-2014

Re: Can VHDL shared variables be synthesized?

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@anusheel,

yes I know!

My code also used shared variables but synthesis engine complains, why?

 

Remember my requirement is : True DP Asym Block RAM Write First

 

@geoffbarnes, just copy + paste my code in Vivado and try synth it! 

Non-protected shared variable is used :

shared variable my_ram : ramType := (others => (others => '0'));
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Explorer
Explorer
2,459 Views
Registered: ‎09-07-2011

Re: Can VHDL shared variables be synthesized?

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Don't have 2017.4.. but 2016.2 spit out a RAMB18E1 ....

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Moderator
Moderator
3,532 Views
Registered: ‎03-16-2017

Re: Can VHDL shared variables be synthesized?

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Hi @dpaul24,

 

Change the type of your .vhd file to VHDL instead of VHDL 2008. (As shown below.)

 

Capt55ure.JPG

 

Regards,

hemangd

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
Scholar dpaul24
Scholar
2,452 Views
Registered: ‎08-07-2014

Re: Can VHDL shared variables be synthesized?

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@hemangdand others,

 

Yes changing it from VHDL2008 to VHDL works! Thanks a lot.

 

But why is this support not available in VHDL2008?

I always use VHDL2008 by default. It was not intuitive for me (other non-Xilinx members too I guess) to make such a change unless specifically told. Also no Xilinx docu mentions this. At least a small note can be put to UG901 on this.

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Scholar richardhead
Scholar
2,413 Views
Registered: ‎08-01-2012

Re: Can VHDL shared variables be synthesized?

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@dpaul

In the VHDL 2002 (and onwards LRM) shared variables must be of a protected type (which likely wont be synthesisable)

It seems odd Xilinx have chosen to follow the LRM on this, when all sim tools by default demote this to a warning and just work anyway to maintain backwards compatability (and xilinx supports hardly any of VHDL 2008). It would also be nice to bring in 2008 features and still allow inference of write-first BRAM.
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Explorer
Explorer
2,399 Views
Registered: ‎09-07-2011

Re: Can VHDL shared variables be synthesized?

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Vivado also seems OK with this 2-clock process, which breaks from tradition ... avoids shared variable so is VHDL version agnostic..

Not sure if this just works by accident, or actually supported by the tool.   In general, can't think of why it shouldn't be. 

   process (clkA,clkB)
         variable my_ram : ramType := (others => (others => '0'));
    begin
      if rising_edge(clkA) then
        if enA = '1' then
          ...
        end if;
        regA <= readA;
      end if;

      if rising_edge(clkB) then
          for i in 0 to RATIO-1 loop
              if enB = '1' then        
                 ...
              end if;
          end loop;
          regB <= readB;
      end if;
    end process;
Scholar richardhead
Scholar
2,394 Views
Registered: ‎08-01-2012

Re: Can VHDL shared variables be synthesized?

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I have found several odd bits of code over the years for Altera (where I have more experience) that seemed odd but worked. Below is a quick example (not good coding practice!):

 

-- Synthesises a register when d not in sensitivity list, else a latch.
process(clk)
begin
  if clk = '1' then
    q <= d;
  end if;
end process;

So interestingly, after years of being told that we should ignore sensitivity lists for synthesis, it appears quartus has started looking at them.

 

The above code always gives me a latch in vivado 2017.2

Explorer
Explorer
1,204 Views
Registered: ‎09-07-2011

Re: Can VHDL shared variables be synthesized?

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Yeah that's a little weird.  It confused me a little first looking at it..

 

I flip-flopped on the idea that it should be a latch, then I latched onto the idea that it can only be a flip-flop.    Altera has it right.

 

 

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