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1,266 Views
Registered: ‎04-11-2017

Can any one let me know the differences ?

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First case : 

 

 

wire [7:0]divisor;

wire [1:0] result;
assign result = divisor[5:6];

In this case getting following ERROR: [Synth 8-523] part-select [5:6] does not match declaration 

 

Second Case : 

wire [7:0]divisor;

wire [1:0] result;
assign result = {divisor[5],divisor[6]};

In this case no error is observed ?

 

 

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Moderator
Moderator
1,110 Views
Registered: ‎05-31-2017

Re: Can any one let me know the differences ?

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Hi @anjaneyulu.challa9,

 

You should not specify the reverse range for accessing when compared with the declaration.

For example in the below code you have specified MSB as 7 and LSB as 0 (higher to lower) while declaring the divisor signal and when it did come for accessing you have reversed the range MSB as 5 abd LSB as 6 (lower to higher) which is not valid.

wire [7:0]divisor;

wire [1:0] result;
assign result = divisor[5:6];

So, you should make sure that you are not reversing the range when accessing while compared to the declaration.

 

To overcome this you need to change the range direction  either during declaration or at accessing so that both matches.

 

Now in the other scenario below, you are not selecting the range but you are concatenating the individual bits so you won't see error in this case.

wire [7:0]divisor;

wire [1:0] result;
assign result = {divisor[5],divisor[6]};    

 Hope this helps.

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8 Replies
Adventurer
Adventurer
1,262 Views
Registered: ‎11-13-2017

Re: Can any one let me know the differences ?

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Should it not be 6:5, since you declared the wire as 7:0? I.e. MSB first.

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1,260 Views
Registered: ‎04-11-2017

Re: Can any one let me know the differences ?

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@logictable tried both ways seeing same error
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Xilinx Employee
Xilinx Employee
1,216 Views
Registered: ‎03-30-2016

Re: Can any one let me know the differences ?

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Hello all,

 

Just tried to synthesis the following test module using Vivado 2018.2.

No Error, No critical warning.


module TOP_XC (DIV, RES );
input [7:0] DIV;
output [1:0] RES;

wire [7:0]divisor;
wire [1:0] result;

assign result = {divisor[5],divisor[6]};
assign RES = result;
assign divisor = DIV;
endmodule

 

@anjaneyulu.challa9

I suspected your RTL is using complicated parameter to define signal bitwidth.

 

Please check it carefully, it may fix the issue.

 

Thanks & regards
Leo

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1,206 Views
Registered: ‎04-11-2017

Re: Can any one let me know the differences ?

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@karnanl Even i am seeing no issues with assign result = {divisor[5],divisor[6]}; seeing the error with 

assign result = divisor[5:6];

  

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Xilinx Employee
Xilinx Employee
1,200 Views
Registered: ‎03-30-2016

Re: Can any one let me know the differences ?

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@anjaneyulu.challa9

 

I suggest you to use the second case, or you may also want to try for-loop syntax if you bus size is too wide.
I do not think Verilog support bit reversal for assignment or signal declaration.
I am not sure, but I think other synthesis tool will also generate similar error/critical warning for your RTL (first-case). 

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Moderator
Moderator
1,143 Views
Registered: ‎05-31-2017

Re: Can any one let me know the differences ?

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Hi @anjaneyulu.challa9,

 

As correctly suggested by @logictable, you need to use divisor[6:5] rather than divisor[5:6]. I did check the same at my end in Vivado 2018.1 and I don't see any errors and the cod eis synthesizing with no issues. If you are using the declaration of type divisor[5:6] then you will see those errors.

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1,126 Views
Registered: ‎04-11-2017

Re: Can any one let me know the differences ?

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@shammeera I knew the working case . I am her to know why the other case is a error ?
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Moderator
Moderator
1,111 Views
Registered: ‎05-31-2017

Re: Can any one let me know the differences ?

Jump to solution

Hi @anjaneyulu.challa9,

 

You should not specify the reverse range for accessing when compared with the declaration.

For example in the below code you have specified MSB as 7 and LSB as 0 (higher to lower) while declaring the divisor signal and when it did come for accessing you have reversed the range MSB as 5 abd LSB as 6 (lower to higher) which is not valid.

wire [7:0]divisor;

wire [1:0] result;
assign result = divisor[5:6];

So, you should make sure that you are not reversing the range when accessing while compared to the declaration.

 

To overcome this you need to change the range direction  either during declaration or at accessing so that both matches.

 

Now in the other scenario below, you are not selecting the range but you are concatenating the individual bits so you won't see error in this case.

wire [7:0]divisor;

wire [1:0] result;
assign result = {divisor[5],divisor[6]};    

 Hope this helps.

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