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Visitor
Visitor
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Registered: ‎03-15-2016

Can not mapped to RAM because it is too sparse

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Hi!

 

I want to synthesize the metadata array of a 32-way 2MB cache. Below is the code.

 

module T_10933_ext(
  input W0_clk,
  input [9:0] W0_addr,
  input W0_en,
  input [639:0] W0_data,
  input [31:0] W0_mask,
  input R0_clk,
  input [9:0] R0_addr,
  input R0_en,
  output [639:0] R0_data
);

  reg [9:0] reg_R0_addr;
  reg [639:0] ram [1023:0];
  always @(posedge R0_clk)
    if (R0_en) reg_R0_addr <= R0_addr;
  always @(posedge W0_clk)
    if (W0_en) begin
      if (W0_mask[0]) ram[W0_addr][19:0] <= W0_data[19:0];
      if (W0_mask[1]) ram[W0_addr][39:20] <= W0_data[39:20];
      if (W0_mask[2]) ram[W0_addr][59:40] <= W0_data[59:40];
      if (W0_mask[3]) ram[W0_addr][79:60] <= W0_data[79:60];
      if (W0_mask[4]) ram[W0_addr][99:80] <= W0_data[99:80];
      if (W0_mask[5]) ram[W0_addr][119:100] <= W0_data[119:100];
      if (W0_mask[6]) ram[W0_addr][139:120] <= W0_data[139:120];
      if (W0_mask[7]) ram[W0_addr][159:140] <= W0_data[159:140];
      if (W0_mask[8]) ram[W0_addr][179:160] <= W0_data[179:160];
      if (W0_mask[9]) ram[W0_addr][199:180] <= W0_data[199:180];
      if (W0_mask[10]) ram[W0_addr][219:200] <= W0_data[219:200];
      if (W0_mask[11]) ram[W0_addr][239:220] <= W0_data[239:220];
      if (W0_mask[12]) ram[W0_addr][259:240] <= W0_data[259:240];
      if (W0_mask[13]) ram[W0_addr][279:260] <= W0_data[279:260];
      if (W0_mask[14]) ram[W0_addr][299:280] <= W0_data[299:280];
      if (W0_mask[15]) ram[W0_addr][319:300] <= W0_data[319:300];
      if (W0_mask[16]) ram[W0_addr][339:320] <= W0_data[339:320];
      if (W0_mask[17]) ram[W0_addr][359:340] <= W0_data[359:340];
      if (W0_mask[18]) ram[W0_addr][379:360] <= W0_data[379:360];
      if (W0_mask[19]) ram[W0_addr][399:380] <= W0_data[399:380];
      if (W0_mask[20]) ram[W0_addr][419:400] <= W0_data[419:400];
      if (W0_mask[21]) ram[W0_addr][439:420] <= W0_data[439:420];
      if (W0_mask[22]) ram[W0_addr][459:440] <= W0_data[459:440];
      if (W0_mask[23]) ram[W0_addr][479:460] <= W0_data[479:460];
      if (W0_mask[24]) ram[W0_addr][499:480] <= W0_data[499:480];
      if (W0_mask[25]) ram[W0_addr][519:500] <= W0_data[519:500];
      if (W0_mask[26]) ram[W0_addr][539:520] <= W0_data[539:520];
      if (W0_mask[27]) ram[W0_addr][559:540] <= W0_data[559:540];
      if (W0_mask[28]) ram[W0_addr][579:560] <= W0_data[579:560];
      if (W0_mask[29]) ram[W0_addr][599:580] <= W0_data[599:580];
      if (W0_mask[30]) ram[W0_addr][619:600] <= W0_data[619:600];
      if (W0_mask[31]) ram[W0_addr][639:620] <= W0_data[639:620];
    end
  assign R0_data = ram[reg_R0_addr];

endmodule

However, I get the following information during synthesis.

 

INFO: [Synth 8-5546] ROM "ram_reg[1023]" won't be mapped to RAM because it is too sparse

INFO: [Synth 8-5546] ROM "ram_reg[1022]" won't be mapped to RAM because it is too sparse

...

INFO: [Synth 8-5546] ROM "ram_reg[0]" won't be mapped to RAM because it is too sparse

 

And the synthesis result shows that this code consumes 198848 LUTs and 622873 FFs!

 

But when I change it to a 16-way 2MB cache, the "too sparse" information does not appear, and the "ram" variable can be mapped RAMs successfully. Below is the code for the 16-way cache. This code only consumes 11 LUTs, 11 FFs and 24 BRAMs

 

module T_6517_ext(
  input W0_clk,
  input [10:0] W0_addr,
  input W0_en,
  input [303:0] W0_data,
  input [15:0] W0_mask,
  input R0_clk,
  input [10:0] R0_addr,
  input R0_en,
  output [303:0] R0_data
);

  reg [10:0] reg_R0_addr;
  reg [303:0] ram [2047:0];
  always @(posedge R0_clk)
    if (R0_en) reg_R0_addr <= R0_addr;
  always @(posedge W0_clk)
    if (W0_en) begin
      if (W0_mask[0]) ram[W0_addr][18:0] <= W0_data[18:0];
      if (W0_mask[1]) ram[W0_addr][37:19] <= W0_data[37:19];
      if (W0_mask[2]) ram[W0_addr][56:38] <= W0_data[56:38];
      if (W0_mask[3]) ram[W0_addr][75:57] <= W0_data[75:57];
      if (W0_mask[4]) ram[W0_addr][94:76] <= W0_data[94:76];
      if (W0_mask[5]) ram[W0_addr][113:95] <= W0_data[113:95];
      if (W0_mask[6]) ram[W0_addr][132:114] <= W0_data[132:114];
      if (W0_mask[7]) ram[W0_addr][151:133] <= W0_data[151:133];
      if (W0_mask[8]) ram[W0_addr][170:152] <= W0_data[170:152];
      if (W0_mask[9]) ram[W0_addr][189:171] <= W0_data[189:171];
      if (W0_mask[10]) ram[W0_addr][208:190] <= W0_data[208:190];
      if (W0_mask[11]) ram[W0_addr][227:209] <= W0_data[227:209];
      if (W0_mask[12]) ram[W0_addr][246:228] <= W0_data[246:228];
      if (W0_mask[13]) ram[W0_addr][265:247] <= W0_data[265:247];
      if (W0_mask[14]) ram[W0_addr][284:266] <= W0_data[284:266];
      if (W0_mask[15]) ram[W0_addr][303:285] <= W0_data[303:285];
    end
  assign R0_data = ram[reg_R0_addr];

endmodule

I can not figure out how to deal with the "too sparse" issue, since the pattern of the 16-way code and the 32-way code is similar.

 

Can anyone provide some suggestions?

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Xilinx Employee
Xilinx Employee
13,440 Views
Registered: ‎02-16-2014

Re: Can not mapped to RAM because it is too sparse

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Hi @worseworst

 

I am able to reproduce the issue at my end. Tested in 2016.4 internal build and I see the same behaviour.

Tried applying ram_style = block attribute but this does not have any effect.

Looks like an issue with the tool.Investigating the issue further and will keep you posted.

 

 

View solution in original post

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Xilinx Employee
Xilinx Employee
8,115 Views
Registered: ‎04-16-2012

Re: Can not mapped to RAM because it is too sparse

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Hi @worseworst

 

Check this forums thread on the same issue: https://forums.xilinx.com/t5/Welcome-Join/Vivado-2015-1-not-inferring-RAM-with-attribute-ram-style-set/td-p/642525

This issue was seen when Vivado template guidelines are not followed.

 

Thanks,

Vinay

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Visitor
Visitor
8,096 Views
Registered: ‎03-15-2016

Re: Can not mapped to RAM because it is too sparse

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Hi @vuppala

 

Thank you for the reply! I think this issue is unrelated to the Vivado template, since the 16-way code and the 32-way code follow the same template, but the 16-way code is ok and 32-way code is not. This confuses me.

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Xilinx Employee
Xilinx Employee
13,441 Views
Registered: ‎02-16-2014

Re: Can not mapped to RAM because it is too sparse

Jump to solution

Hi @worseworst

 

I am able to reproduce the issue at my end. Tested in 2016.4 internal build and I see the same behaviour.

Tried applying ram_style = block attribute but this does not have any effect.

Looks like an issue with the tool.Investigating the issue further and will keep you posted.

 

 

View solution in original post

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Moderator
Moderator
7,975 Views
Registered: ‎07-21-2014

Re: Can not mapped to RAM because it is too sparse

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@worseworst

 

I think due to big mux logic coming from if-statement tool is not able to absorb it into the BRAM. Tool should use more than 30 BRAMs to infer the above logic. 

 

Thanks,
Anusheel
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Visitor
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Registered: ‎03-15-2016

Re: Can not mapped to RAM because it is too sparse

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Hi @pulim

 

Thank you for the testing! It seems that this issue can not be solved in the current version. Anyway, I can use the 16-way code. :)

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Visitor
Visitor
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Registered: ‎03-15-2016

Re: Can not mapped to RAM because it is too sparse

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Hi @anusheel

 

Your consideration makes sense. I will use the 16-way code to avoid this issue. Thank you!

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