My problem is when I insert a chipscope atc2 core into my design (edf by Synplify Preimier), timing result is too bad that P&R command (Script operation) stop excute.
My design includes a CPU core and some peripherals, first I use synplify tools syn_probe attribute add in some signals to probe in the outside, then since the I/O limitation, I try to use ChipScope Agilent core ATC2 inserter in my design in order to use bank selection style to probe the internal signals
However, when the cdc file is added, the ISE report the timing is too bad to stop excute P&R job.
How can I do in this case, because it is a real system, the main clock can't slow down to fit for FPGA debug. And use syn_probe way has no timing violations for the previous design.