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Visitor tanvirheer
Visitor
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Registered: ‎06-25-2018

Clock Question: Artix-A7 35T - Clocking wizard or Verilog?

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Board: Artix-A7 35T.

Datasheet: https://reference.digilentinc.com/_media/cmod_a7/cmod_a7_rm.pdf

 

The Artix Cmod A7 35T FPGA has a single 12 MHz clock input connected to pin L17 (L17 is a MRCC input on bank 14). The input clock can drive MMCMs to generate clocks of various frequencies.

 

I want it to output 1 MHz Clk. Now, do I instantiate this via the clocking wizard within vivado? Currently, I'm writing my logic in ModelSim and was wondering if I have to instantiate this in RTL Verilog. What I mean by this is, do I have to worry about instantiating clocking system  as: 

wire          osc_12mhz;

BUFG osc_12mhz(.PAD(OSC_12MHZ), .Y(osc_12mhz));

 

I am just a little confused if I even have to implement this at all or just simply use the clocking wizard to handle it. The reason is, what if this logic is implemented on a different FPGA in the near future, therefore I wanted to automate it somehow within the Verilog.

 

Essentially, the end goal is just to simply output 1MHz clock from this FPGA, maybe someone can explain this conceptually.

 

Let me know, Thanks.

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“If you want to find the secrets of the universe, think in terms of energy, frequency and vibration.” ― Nikola Tesla
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Scholar dpaul24
Scholar
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Registered: ‎08-07-2014

Re: Clock Question: Artix-A7 35T - Clocking wizard or Verilog?

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@tanvirheer,

 

Now, do I instantiate this via the clocking wizard within vivado?

Yes.

 

All have to do is just instiantiate the clock wizard after you have added the clock wizard IP core to your project.

But make sure that the MMCM/PLL inside the clock wizard is capable of generating 1MHz from 12MHz (most of them have a range, and you intended o/p frq must be within that range).

 

If 1MHz is not supported, then you must do a divide-by-12 operation in Verilog to your incoming 12MHz clock to get 1 MHz.

 

Don't worry about the BUFG and its instiantiation. It will be automatically inserted by Vivado synthesis engine at the proper place, which will not affect your RTL.

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3 Replies
Scholar dpaul24
Scholar
803 Views
Registered: ‎08-07-2014

Re: Clock Question: Artix-A7 35T - Clocking wizard or Verilog?

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@tanvirheer,

 

Now, do I instantiate this via the clocking wizard within vivado?

Yes.

 

All have to do is just instiantiate the clock wizard after you have added the clock wizard IP core to your project.

But make sure that the MMCM/PLL inside the clock wizard is capable of generating 1MHz from 12MHz (most of them have a range, and you intended o/p frq must be within that range).

 

If 1MHz is not supported, then you must do a divide-by-12 operation in Verilog to your incoming 12MHz clock to get 1 MHz.

 

Don't worry about the BUFG and its instiantiation. It will be automatically inserted by Vivado synthesis engine at the proper place, which will not affect your RTL.

--------------------------------------------------------------------------------------------------------
FPGA enthusiast!
All PMs will be ignored
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Visitor tanvirheer
Visitor
666 Views
Registered: ‎06-25-2018

Re: Clock Question: Artix-A7 35T - Clocking wizard or Verilog?

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@dpaul24

 

Thank you for the reply. I am just recently starting learning verilog and working with FPGAs, so this clears it out. I guess for more complex projects or boards, I would probably have to worry about instantiating clocks within the verilog logic.

 

So, I can simply assume in my verilog logic for the time being that I already have the 1MHz Clock signal and use that rather than writing some logic that does frequency division from 12 -> 1 MHz. Correct?

 

Otherwise, thank you. I believe my question is answered then. The datasheet about clocking systems was hundreds of pages long, the one provided by Xilinx. Therefore, it sort of got confusing and overwhelming looking at all these different clock systems.

--------------------------------------------------------------------------------------
“If you want to find the secrets of the universe, think in terms of energy, frequency and vibration.” ― Nikola Tesla
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Scholar dpaul24
Scholar
631 Views
Registered: ‎08-07-2014

Re: Clock Question: Artix-A7 35T - Clocking wizard or Verilog?

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@tanvirheer,

I guess for more complex projects or boards, I would probably have to worry about instantiating clocks within the verilog logic.

Yes, instantiating the "clocking wizard".

 

So, I can simply assume in my verilog logic for the time being that I already have the 1MHz Clock signal and use that rather than writing some logic that does frequency division from 12 -> 1 MHz. Correct?

For developing the core design, yes.

But if you want to implement this design on a FPGA board, then you have to come to this clock part.

 

 

 

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