cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Explorer
Explorer
528 Views
Registered: ‎09-08-2009

Coding Guideline

Jump to solution

 

https://www.xilinx.com/support/documentation/white_papers/wp275.pdf

is page 8 still valid for Vivado 2018.3 ? (Spartan 7)

 

 

0 Kudos
1 Solution

Accepted Solutions
Highlighted
386 Views
Registered: ‎01-22-2015

@999068709169 

As Richard says, both Version-1 and Version-2 give identical synthesis results, which are:
a_b_output.jpg

I agree with Richard that “making readable code” should be your selection criteria.

If you come from a software (C++, HLS) background then I suspect you will select Version-1.  However, if you come from a digital hardware background then you’ll probably choose Version-2.

My personal preference is Version-2 because it is a direct reference to the digital combinational logic found in the LUT2 resulting from synthesis.  -and, since we are using VHDL (a hardware descriptive language) then we should be “thinking hardware” as we write our code.

Cheers,
Mark

View solution in original post

6 Replies
Highlighted
Scholar
Scholar
506 Views
Registered: ‎08-01-2012

Yes. That example is just a general coding statement that is pretty valid for all devices. 

Do you have a specific question?

0 Kudos
Highlighted
Explorer
Explorer
471 Views
Registered: ‎09-08-2009

@richardhead 

Xilinx recommends version1 or version2?

Version 1

if rising_edge(clk) then
    if (a ='1' and b = '0') then
        output <= '1';
    else
        output <= '0';
    end if;
end if;

Version 2

if rising_edge(clk) then
        output <= a and (not b);
end if;
0 Kudos
Highlighted
Moderator
Moderator
460 Views
Registered: ‎03-16-2017

Hi @999068709169 , 

version 1. 

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
0 Kudos
Highlighted
Scholar
Scholar
443 Views
Registered: ‎08-01-2012

@999068709169 

Those are functionally identical and will give identical synthesis results.

The paper talks more about Set and Reset of the built in flops. Your code example does not.

Code with the style you find (and others will find) most readible. Synthesis is very good today and its much better to have a readible style than "tool friendly" style from 2007. 

Highlighted
Explorer
Explorer
409 Views
Registered: ‎09-08-2009

@hemangd you are suggesting version 1 whereas @richardhead says "does not matter just write readable code". Do you have some explanation?

0 Kudos
Highlighted
387 Views
Registered: ‎01-22-2015

@999068709169 

As Richard says, both Version-1 and Version-2 give identical synthesis results, which are:
a_b_output.jpg

I agree with Richard that “making readable code” should be your selection criteria.

If you come from a software (C++, HLS) background then I suspect you will select Version-1.  However, if you come from a digital hardware background then you’ll probably choose Version-2.

My personal preference is Version-2 because it is a direct reference to the digital combinational logic found in the LUT2 resulting from synthesis.  -and, since we are using VHDL (a hardware descriptive language) then we should be “thinking hardware” as we write our code.

Cheers,
Mark

View solution in original post