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Visitor
Visitor
9,388 Views
Registered: ‎11-15-2016

Combinational loop (Ring oscillator)

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Hey Guys

 

 

Previously I have used ISE Design Suite and I had no problem with my code but now with VIVADO there are some issues. my code generates a ring oscillator which is a combinational loop. When I want to  generate bitstream I receive this error:

 

ERROR: [DRC 23-20] Rule violation (LUTLP-1) Combinatorial Loop Alert - 1 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. If the loop is known and understood, this DRC can be bypassed by acknowledging the condition and setting the following XDC constraint on any net in the loop: 'set_property ALLOW_COMBINATORIAL_LOOPS TRUE [net_nets <myHier/myNet>'. The cells in the loop are: PUF_array/PUF_GEN[0].Ring_osc/out0_inferred_i_1.

 

can you please hel me how to get rid of this error?

 

Thanx for your time

Bests!

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Xilinx Employee
Xilinx Employee
16,321 Views
Registered: ‎08-01-2008

Re: Combinational loop (Ring oscillator)

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DRC check only enabled in Vivado tool . Check this related post

https://forums.xilinx.com/t5/Implementation/DRC-23-20-Rule-Violation-LUTLP-1/td-p/674253
Thanks and Regards
Balkrishan
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Xilinx Employee
Xilinx Employee
16,322 Views
Registered: ‎08-01-2008

Re: Combinational loop (Ring oscillator)

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DRC check only enabled in Vivado tool . Check this related post

https://forums.xilinx.com/t5/Implementation/DRC-23-20-Rule-Violation-LUTLP-1/td-p/674253
Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.

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Scholar
Scholar
9,372 Views
Registered: ‎02-27-2008

Re: Combinational loop (Ring oscillator)

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a,

 

You can right click on the error, and change it to a warning using the Vivado GUI, or create a TCL command to do the same.

 

https://www.xilinx.com/support/answers/53981.html

Austin Lesea
Principal Engineer
Xilinx San Jose
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Visitor
Visitor
9,300 Views
Registered: ‎11-15-2016

Re: Combinational loop (Ring oscillator)

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Thanks guys!

 

It solved! :)

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Contributor
Contributor
8,963 Views
Registered: ‎04-19-2016

Re: Combinational loop (Ring oscillator)

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You can also get round it by declaring the net of your ring oscillator like this:

(* ALLOW_COMBINATORIAL_LOOPS = "true", KEEP = "true" *) wire [BITS-1:0] ring;
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8,938 Views
Registered: ‎01-08-2012

Re: Combinational loop (Ring oscillator)

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@patstew wrote:
(* ALLOW_COMBINATORIAL_LOOPS = "true", KEEP = "true" *) wire [BITS-1:0] ring;

Where is that attribute documented?  I would like to read more about it.

 

Thanks,

Allan

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