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Newbie
Newbie
396 Views
Registered: ‎05-20-2016

[Common 17-69] Command failed: Unable to run synthesis. No HDL sources found in project

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Hi,

I have a project that gives OOC synthesis errors when I try to build it. It worked fine for weeks. The missing source files are related to an AXI interconnect. I've tried reseting the IP.

Are there any other ideas?

Thanks,

Winefred

 

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Xilinx Employee
Xilinx Employee
365 Views
Registered: ‎05-14-2008

Try "Generate Output Product" in the right click menu for this IP.

-vivian

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Highlighted
Xilinx Employee
Xilinx Employee
366 Views
Registered: ‎05-14-2008

Try "Generate Output Product" in the right click menu for this IP.

-vivian

-------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
-------------------------------------------------------------------------------------------------

View solution in original post

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