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Registered: ‎05-09-2020

Compare 2D Arrays In Verilog

Whats the best way to compare two 2D arrays in Verilog or SystemVerilog in parallel?

Below code doesn't synthesize.

 

wire [7:0] a[0:50];
wire [7:0] b[0:50];
output reg same=0; always @ (posedge clock) begin if(a == b) begin same <=1; end
else
same <=0;
end end

Cheers

 

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Scholar
Scholar
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Registered: ‎05-21-2015

Re: Compare 2D Arrays In Verilog

@xilinxuser005,

Start at the beginning: how are the arrays coming into your design?

  • Do they exist externally in memory?  This would be appropriate for a large array.  Such large 2D arrays would likely be stored as a large chunk of memory, which could then be compared as a two streams.
  • Are the arrays small enough that they can both fit in single registers?  Like your example, but imagine reg [8*64-1:0] A, B.  Then your method below will work.
  • If the array is small enough to fit on chip, but too big to fit in flip-flops, then you'd write the definitions of the array elements as you've done above.  In that case, you'd need to read from one element at a time to do your comparison as well.

Bottom line: let the hardware you have and the problem statement dictate the appropriate answer, not the language you are using to express it.

Dan

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Scholar
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Registered: ‎09-16-2009

Re: Compare 2D Arrays In Verilog

Please describe what you mean by "Doesn't Synthesize"?

Does Vivado error out?  If so what is the error message?  Does it work in simulation?

Does it produce logic in which the netlist doesn't match the RTL?  If so please desribe what you think the differences are.

Regards,

Mark

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