05-09-2020 12:56 AM - edited 05-09-2020 01:55 AM
Whats the best way to compare two 2D arrays in Verilog or SystemVerilog in parallel?
Below code doesn't synthesize.
wire [7:0] a[0:50]; wire [7:0] b[0:50];
output reg same=0; always @ (posedge clock) begin if(a == b) begin same <=1; end
05-09-2020 08:32 PM
Start at the beginning: how are the arrays coming into your design?
Bottom line: let the hardware you have and the problem statement dictate the appropriate answer, not the language you are using to express it.
05-11-2020 10:04 AM
Please describe what you mean by "Doesn't Synthesize"?
Does Vivado error out? If so what is the error message? Does it work in simulation?
Does it produce logic in which the netlist doesn't match the RTL? If so please desribe what you think the differences are.